300 lines
12 KiB
C
300 lines
12 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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* 2014-04-03 Grissiom many enhancements
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* 2018-11-22 Jesven add rt_hw_ipi_send()
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* add rt_hw_ipi_handler_install()
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* 2023-02-01 GuEe-GUI move macros to header
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*/
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#ifndef __IRQ_GICV3_H__
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#define __IRQ_GICV3_H__
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#include <rtdef.h>
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#include <cpuport.h>
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#include <drivers/pic.h>
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#include <drivers/core/dm.h>
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#include <dt-bindings/size.h>
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/* Distributor registers */
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_TYPER2 0x000C
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#define GICD_STATUSR 0x0010
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#define GICD_SETSPI_NSR 0x0040
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#define GICD_CLRSPI_NSR 0x0048
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ISPENDR 0x0200
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#define GICD_ICPENDR 0x0280
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#define GICD_ISACTIVER 0x0300
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#define GICD_ICACTIVER 0x0380
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#define GICD_IPRIORITYR 0x0400
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#define GICD_ICFGR 0x0C00
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#define GICD_IGRPMODR 0x0D00
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#define GICD_NSACR 0x0E00
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#define GICD_IGROUPRnE 0x1000
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#define GICD_ISENABLERnE 0x1200
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#define GICD_ICENABLERnE 0x1400
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#define GICD_ISPENDRnE 0x1600
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#define GICD_ICPENDRnE 0x1800
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#define GICD_ISACTIVERnE 0x1A00
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#define GICD_ICACTIVERnE 0x1C00
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#define GICD_IPRIORITYRnE 0x2000
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#define GICD_ICFGRnE 0x3000
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#define GICD_IROUTER 0x6000
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#define GICD_IROUTERnE 0x8000
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#define GICD_IDREGS 0xFFD0
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#define GICD_PIDR2 0xFFE8
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#define GICD_ITARGETSR 0x0800
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#define GICD_SGIR 0x0F00
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#define GICD_CPENDSGIR 0x0F10
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#define GICD_SPENDSGIR 0x0F20
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_nASSGIreq (1U << 8)
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#define GICD_CTLR_DS (1U << 6)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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#define GICD_TYPER_RSS (1U << 26)
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#define GICD_TYPER_LPIS (1U << 17)
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#define GICD_TYPER_MBIS (1U << 16)
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#define GICD_TYPER_ESPI (1U << 8)
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#define GICD_TYPER_ID_BITS(t) ((((t) >> 19) & 0x1f) + 1)
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#define GICD_TYPER_NUM_LPIS(t) ((((t) >> 11) & 0x1f) + 1)
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#define GICD_TYPER_SPIS(t) ((((t) & 0x1f) + 1) * 32)
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#define GICD_TYPER_ESPIS(t) (((t) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((t) >> 27) : 0)
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/* Redistributor registers */
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#define GICR_CTLR 0x0000
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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#define GICR_MPAMIDR 0x0018
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#define GICR_PARTIDR 0x001C
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#define GICR_SETLPIR 0x0040
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#define GICR_CLRLPIR 0x0048
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#define GICR_PROPBASER 0x0070
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#define GICR_PENDBASER 0x0078
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#define GICR_INVLPIR 0x00A0
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#define GICR_INVALLR 0x00B0
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#define GICR_SYNCR 0x00C0
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
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#define GICR_CTLR_CES (1UL << 1)
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#define GICR_CTLR_IR (1UL << 2)
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#define GICR_CTLR_RWP (1UL << 3)
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#define GICR_RD_BASE_SIZE (64 * SIZE_KB)
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#define GICR_SGI_OFFSET (64 * SIZE_KB)
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#define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET
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/* Re-Distributor registers, offsets from SGI_base */
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#define GICR_IGROUPR0 GICD_IGROUPR
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#define GICR_ISENABLER0 GICD_ISENABLER
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#define GICR_ICENABLER0 GICD_ICENABLER
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#define GICR_ISPENDR0 GICD_ISPENDR
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#define GICR_ICPENDR0 GICD_ICPENDR
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#define GICR_ISACTIVER0 GICD_ISACTIVER
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#define GICR_ICACTIVER0 GICD_ICACTIVER
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#define GICR_IPRIORITYR0 GICD_IPRIORITYR
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#define GICR_ICFGR0 GICD_ICFGR
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#define GICR_IGRPMODR0 GICD_IGRPMODR
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#define GICR_NSACR GICD_NSACR
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_DIRTY (1U << 2)
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#define GICR_TYPER_DirectLPIS (1U << 3)
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#define GICR_TYPER_LAST (1U << 4)
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#define GICR_TYPER_RVPEID (1U << 7)
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#define GICR_TYPER_COM_LPI_AFF RT_GENMASK_ULL(25, 24)
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#define GICR_TYPER_AFFINITY RT_GENMASK_ULL(63, 32)
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#define GICR_INVLPIR_INTID RT_GENMASK_ULL(31, 0)
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#define GICR_INVLPIR_VPEID RT_GENMASK_ULL(47, 32)
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#define GICR_INVLPIR_V RT_GENMASK_ULL(63, 63)
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#define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID
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#define GICR_INVALLR_V GICR_INVLPIR_V
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#define GICR_VLPI_BASE_SIZE (64 * SIZE_KB)
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#define GICR_RESERVED_SIZE (64 * SIZE_KB)
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#define GIC_V3_REDIST_SIZE 0x20000
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#define GICR_TYPER_NR_PPIS(t) (16 + ({ int __ppinum = (((t) >> 27) & 0x1f); __ppinum <= 2 ? __ppinum : 0; }) * 32)
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#define GICR_WAKER_ProcessorSleep (1U << 1)
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#define GICR_WAKER_ChildrenAsleep (1U << 2)
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#define GICR_PROPBASER_IDBITS_MASK (0x1f)
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#define GICR_PROPBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 12))
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#define GICR_PENDBASER_ADDRESS(x) ((x) & RT_GENMASK_ULL(51, 16))
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/* ITS registers */
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#define GITS_CTLR 0x0000
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#define GITS_IIDR 0x0004
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#define GITS_TYPER 0x0008
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#define GITS_MPAMIDR 0x0010
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#define GITS_PARTIDR 0x0014
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#define GITS_MPIDR 0x0018
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#define GITS_STATUSR 0x0040
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#define GITS_UMSIR 0x0048
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#define GITS_CBASER 0x0048
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#define GITS_CWRITER 0x0088
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#define GITS_CREADR 0x0090
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#define GITS_BASER 0x0100 /* 0x0100~0x0138 */
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/*
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* ITS commands
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*/
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#define GITS_CMD_MAPD 0x08
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#define GITS_CMD_MAPC 0x09
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#define GITS_CMD_MAPTI 0x0a
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#define GITS_CMD_MAPI 0x0b
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#define GITS_CMD_MOVI 0x01
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#define GITS_CMD_DISCARD 0x0f
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#define GITS_CMD_INV 0x0c
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#define GITS_CMD_MOVALL 0x0e
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#define GITS_CMD_INVALL 0x0d
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#define GITS_CMD_INT 0x03
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#define GITS_CMD_CLEAR 0x04
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#define GITS_CMD_SYNC 0x05
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/* ITS Config Area */
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#define GITS_LPI_CFG_GROUP1 (1 << 1)
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#define GITS_LPI_CFG_ENABLED (1 << 0)
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/* ITS Command Queue Descriptor */
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#define GITS_CBASER_VALID (1UL << 63)
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#define GITS_CBASER_SHAREABILITY_SHIFT (10)
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#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
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#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
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#define GITS_TRANSLATION_TABLE_DESCRIPTORS_NR 8
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#define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \
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(GITS_CBASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
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#define GITS_BASER_SHAREABILITY(reg, type) \
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(GITS_CBASER_##type << reg##_SHAREABILITY_SHIFT)
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#define GITS_CBASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */
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#define GITS_CBASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */
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#define GITS_CBASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */
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#define GITS_CBASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */
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#define GITS_CBASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */
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#define GITS_CBASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */
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#define GITS_CBASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */
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#define GITS_CBASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */
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#define GITS_CBASER_CACHE_MASK 0x7UL
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#define GITS_CBASER_SHARE_NS 0x0UL /* Non-shareable. */
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#define GITS_CBASER_SHARE_IS 0x1UL /* Inner Shareable. */
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#define GITS_CBASER_SHARE_OS 0x2UL /* Outer Shareable. */
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#define GITS_CBASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */
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#define GITS_CBASER_SHARE_MASK 0x3UL
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#define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS)
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#define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK)
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#define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE)
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#define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN)
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#define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT)
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#define GITS_CBASER_RaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWB)
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#define GITS_CBASER_WaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWT)
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#define GITS_CBASER_WaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIWAWB)
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#define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT)
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#define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB)
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#define GIC_EPPI_BASE_INTID 1056
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#define GIC_ESPI_BASE_INTID 4096
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#define GIC_IRQ_TYPE_LPI 0xa110c8ed
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#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
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#define read_gicreg(reg, out) rt_hw_sysreg_read(reg, out)
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#define write_gicreg(reg, in) rt_hw_sysreg_write(reg, in)
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#define ICC_CTLR_EOImode 0x2
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#define ICC_PMR_MASK 0xff
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#define ICC_PMR_DEFAULT 0xf0
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#define ICC_IGRPEN1_EN 0x1
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#define ICC_SGIR_AFF3_SHIFT 48
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#define ICC_SGIR_AFF2_SHIFT 32
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#define ICC_SGIR_AFF1_SHIFT 16
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#define ICC_SGIR_TARGET_MASK 0xffff
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#define ICC_SGIR_IRQN_SHIFT 24
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#define ICC_SGIR_ROUTING_BIT (1ULL << 40)
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#define ICC_SGI1R_TARGET_LIST_SHIFT 0
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#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
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#define ICC_SGI1R_TARGET_LIST_MAX 16
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#define ICC_SGI1R_AFFINITY_1_SHIFT 16
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#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
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#define ICC_SGI1R_SGI_ID_SHIFT 24
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#define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
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#define ICC_SGI1R_AFFINITY_2_SHIFT 32
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#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
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#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
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#define ICC_SGI1R_RS_SHIFT 44
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#define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
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#define ICC_SGI1R_AFFINITY_3_SHIFT 48
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#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
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#define ICC_CTLR_EL1_CBPR_SHIFT 0
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#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
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#define ICC_CTLR_EL1_EOImode_SHIFT (1)
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#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
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#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
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#define ICC_CTLR_EL1_PRI_BITS_SHIFT (8)
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#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
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#define ICC_CTLR_EL1_RSS (0x1 << 18)
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#define ICC_CTLR_EL1_ExtRange (0x1 << 19)
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struct gicv3
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{
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struct rt_pic parent;
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int version;
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int irq_nr;
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rt_uint32_t gicd_typer;
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rt_size_t line_nr;
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rt_size_t espi_nr;
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rt_size_t lpi_nr;
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rt_ubase_t flags;
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void *dist_base;
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rt_size_t dist_size;
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void *redist_percpu_base[RT_CPUS_NR];
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rt_size_t percpu_ppi_nr[RT_CPUS_NR];
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struct
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{
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void *base;
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void *base_phy;
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rt_size_t size;
|
||
|
|
} *redist_regions;
|
||
|
|
rt_uint64_t redist_flags;
|
||
|
|
rt_size_t redist_stride;
|
||
|
|
rt_size_t redist_regions_nr;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* __IRQ_GICV3_H__ */
|