671 lines
20 KiB
C
671 lines
20 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-25 GuEe-GUI first version
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*/
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#include <rtthread.h>
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#include <drivers/pic.h>
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#include <drivers/ofw.h>
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#include <drivers/ofw_io.h>
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#include <drivers/ofw_irq.h>
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#define DBG_TAG "rtdm.ofw"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include "ofw_internal.h"
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static int ofw_interrupt_cells(struct rt_ofw_node *np)
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{
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int interrupt_cells = -RT_EEMPTY;
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rt_ofw_prop_read_u32(np, "#interrupt-cells", (rt_uint32_t *)&interrupt_cells);
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return interrupt_cells;
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}
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int rt_ofw_irq_cells(struct rt_ofw_node *np)
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{
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return np ? ofw_interrupt_cells(np) : -RT_EINVAL;
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}
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static rt_err_t ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_args *irq_args)
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{
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rt_err_t err = RT_EOK;
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rt_phandle ic_phandle = 0;
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rt_ssize_t map_len, map_mask_len;
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struct rt_ofw_node *ic_np = RT_NULL;
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const fdt32_t *addr, *map, *map_mask;
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int child_address_cells, child_interrupt_cells;
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int parent_address_cells, parent_interrupt_cells;
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int addr_cells, pin_cells, icaddr_cells, idx1, idx2, limit;
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/*
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* interrupt-map:
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* An interrupt-map is a property on a nexus node that bridges one
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* interrupt domain with a set of parent interrupt domains and specifies
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* how interrupt specifiers in the child domain are mapped to
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* their respective parent domains.
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*
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* The interrupt map is a table where each row is a mapping entry
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* consisting of five components: child unit address, child interrupt
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* specifier, interrupt-parent, parent unit address, parent interrupt
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* specifier.
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*
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* child unit address
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* The unit address of the child node being mapped. The number of
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* 32-bit cells required to specify this is described by the
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* #address-cells property of the bus node on which the child is
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* located.
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*
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* child interrupt specifier
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* The interrupt specifier of the child node being mapped. The number
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* of 32-bit cells required to specify this component is described by
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* the #interrupt-cells property of this node-the nexus node containing
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* the interrupt-map property.
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*
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* interrupt-parent
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* A single <phandle> value that points to the interrupt parent to
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* which the child domain is being mapped.
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*
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* parent unit address
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* The unit address in the domain of the interrupt parent. The number
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* of 32-bit cells required to specify this address is described by the
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* #address-cells property of the node pointed to by the
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* interrupt-parent field.
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*
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* parent interrupt specifier
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* The interrupt specifier in the parent domain. The number of 32-bit
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* cells required to specify this component is described by the
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* #interrupt-cells property of the node pointed to by the
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* interrupt-parent field.
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*
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* Lookups are performed on the interrupt mapping table by matching a
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* unit-address/interrupt specifier pair against the child components in
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* the interrupt-map. Because some fields in the unit interrupt specifier
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* may not be relevant, a mask is applied before the lookup is done.
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* Example:
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*
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* pic: interrupt-controller@0 {
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* interrupt-controller;
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* #address-cells = <0>; // icaddr (parent unit address)
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* #interrupt-cells = <1>; // icintr (parent interrupt specifier)
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* };
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*
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* gic: interrupt-controller@1 {
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* interrupt-controller;
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* #address-cells = <2>; // icaddr (parent unit address)
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* #interrupt-cells = <3>; // icintr (parent interrupt specifier)
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* };
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*
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* pcie {
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* #address-cells = <3>; // addr (child unit address)
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* #interrupt-cells = <1>; // pin (child interrupt specifier)
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* interrupt-parent = <&gic>;
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* interrupt-map-mask = <0x1800 0 0 7>;
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* interrupt-map =
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* // addr pin ic icintr
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* <0x0000 0 0 1 &pic 1>, // INTA SOLT 0
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* <0x0000 0 0 2 &pic 2>, // INTB
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* <0x0000 0 0 3 &pic 3>, // INTC
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* <0x0000 0 0 4 &pic 4>, // INTD
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* <0x0800 0 0 1 &pic 2>, // INTA SOLT 1
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* <0x0800 0 0 2 &pic 3>, // INTB
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* <0x0800 0 0 3 &pic 4>, // INTC
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* <0x0800 0 0 4 &pic 1>, // INTD
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* // addr pin ic icaddr icintr
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* <0x1000 0 0 1 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, // INTA SOLT 2
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* <0x1000 0 0 2 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, // INTB
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* <0x1000 0 0 3 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, // INTC
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* <0x1000 0 0 4 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, // INTD
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* <0x1800 0 0 1 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, // INTA SOLT 3
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* <0x1800 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, // INTB
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* <0x1800 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, // INTC
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* <0x1800 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; // INTD
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* };
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*
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* In fact, almost no SoC will be use multi IC to implement INTx.
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* before call ofw_parse_irq_map(np, &args):
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*
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* args.data = addr;
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* args.args_count = 2 or 3;
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* args.args[0] = (addr cells);
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* args.args[1] = (pin cells);
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* args.args[2] = (icaddr cells);
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*
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* if call with `pcie` in ofw_parse_irq_map(np, &args):
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*
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* np = &pcie;
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* args.data = addr = fdt32_t({ (bus << 16) | (device << 11) | (function << 8), 0, 0, pin });
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* args.args_count = 2;
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* args.args[0] = 3;
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* args.args[1] = 1;
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*
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* To perform a lookup of the gic interrupt source number for INTB for IDSEL
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* 0x12 (slot 2), function 0x3, the following steps would be performed:
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*
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* 1.The user addr is value <0x9300 0 0 2>.
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*
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* 2.The encoding of the address includes the bus number (0x0 << 16),
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* device number (0x12 << 11), and function number (0x3 << 8).
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*
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* 3.The interrupt specifier is 2, which is the encoding for INTB as per
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* the PCI binding.
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*
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* 4.The interrupt-map-mask value <0x1800 0 0 7> is applied, giving a
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* result of <0x1000 0 0 2>.
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*
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* 5.That result is looked up in the interrupt-map table, which maps to the
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* parent interrupt specifier <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>.
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*/
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do {
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err = -RT_EEMPTY;
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if ((child_address_cells = rt_ofw_bus_addr_cells(np)) < 0)
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{
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LOG_D("%s property %s is undefined", np->full_name, "#address-cells");
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break;
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}
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if ((child_interrupt_cells = ofw_interrupt_cells(np)) < 0)
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{
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LOG_D("%s property %s is undefined", np->full_name, "#interrupt-cells");
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break;
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}
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if (!(map = rt_ofw_prop_read_raw(np, "interrupt-map", &map_len)))
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{
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LOG_D("%s property %s is undefined", np->full_name, "interrupt-map");
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break;
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}
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if (!(map_mask = rt_ofw_prop_read_raw(np, "interrupt-map-mask", &map_mask_len)))
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{
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LOG_D("%s property %s is undefined", np->full_name, "interrupt-map-mask");
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break;
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}
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map_len = sizeof(fdt32_t);
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map_mask_len = sizeof(fdt32_t);
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err = -RT_EINVAL;
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addr = irq_args->data;
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addr_cells = irq_args->args[0];
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pin_cells = irq_args->args[1];
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icaddr_cells = irq_args->args_count == 3 ? irq_args->args[2] : 0;
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if (addr_cells > child_address_cells)
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{
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LOG_D("%s(%d) > %s(%d)", "addr_cells", addr_cells, "child_address_cells", child_address_cells);
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break;
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}
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if (pin_cells > child_interrupt_cells)
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{
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LOG_D("%s(%d) > %s(%d)", "pin_cells", pin_cells, "child_interrupt_cells", child_interrupt_cells);
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break;
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}
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err = -RT_ENOENT;
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#define _map_walk_range(_idx, _idx2, _count, ...) \
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for (idx1 = _idx, idx2 = _idx2, limit = idx1 + _count; idx1 < limit __VA_ARGS__; ++idx1, ++idx2)
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_map_walk_range(0, 0, addr_cells)
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{
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/* Applied addr mask */
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((fdt32_t *)addr)[idx1] &= map_mask[idx2];
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}
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_map_walk_range(addr_cells, child_address_cells, pin_cells)
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{
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/* Applied pin mask */
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((fdt32_t *)addr)[idx1] &= map_mask[idx2];
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}
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while (map_len > 0)
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{
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rt_bool_t match = RT_TRUE;
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_map_walk_range(0, 0, addr_cells)
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{
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/* Applied mask */
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if (addr[idx1] != map[idx2])
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{
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match = RT_FALSE;
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break;
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}
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}
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_map_walk_range(addr_cells, child_address_cells, pin_cells, && match)
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{
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/* Applied mask */
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if (addr[idx1] != map[idx2])
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{
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match = RT_FALSE;
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break;
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}
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}
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/* Skip addr, pin */
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map += map_mask_len;
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/* IC is different? */
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if (ic_phandle != fdt32_to_cpu(*map))
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{
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rt_ofw_node_put(ic_np);
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ic_phandle = fdt32_to_cpu(*map);
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ic_np = rt_ofw_find_node_by_phandle(ic_phandle);
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if (!ic_np)
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{
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LOG_D("%s irq parent phandle = %d is not found", np->full_name, ic_phandle);
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break;
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}
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if ((parent_address_cells = rt_ofw_bus_addr_cells(ic_np)) < 0)
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{
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LOG_D("%s property %s is undefined", ic_np->full_name, "#address-cells");
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break;
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}
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if (icaddr_cells > parent_address_cells)
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{
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LOG_D("%s(%d) > %s(%d)", "icaddr_cells", icaddr_cells, "parent_address_cells", parent_address_cells);
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break;
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}
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if ((parent_interrupt_cells = ofw_interrupt_cells(ic_np)) < 0)
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{
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LOG_D("%s property %s is undefined", ic_np->full_name, "#interrupt-cells");
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break;
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}
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RT_ASSERT(parent_interrupt_cells <= RT_OFW_MAX_CELL_ARGS);
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}
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/* Skip ic phandle */
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++map;
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_map_walk_range(addr_cells + pin_cells, 0, icaddr_cells, && match)
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{
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/* Applied ic_addr mask */
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if (addr[idx1] != map[idx2])
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{
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match = RT_FALSE;
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break;
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}
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}
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/* Skip icaddr */
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map += parent_address_cells;
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if (match)
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{
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irq_args->data = ic_np;
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irq_args->args_count = parent_interrupt_cells;
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for (int i = 0; i < irq_args->args_count; ++i)
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{
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irq_args->args[i] = fdt32_to_cpu(*map++);
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}
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err = RT_EOK;
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break;
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}
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/* Skip icintr */
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map += parent_interrupt_cells;
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map_len -= map_mask_len + 1 + parent_address_cells + parent_interrupt_cells;
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}
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#undef _map_walk_range
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} while (0);
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return err;
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}
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rt_err_t rt_ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_args *irq_args)
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{
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rt_err_t err;
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if (np && irq_args && irq_args->data)
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{
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err = ofw_parse_irq_map(np, irq_args);
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}
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else
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{
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err = -RT_EINVAL;
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}
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return err;
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}
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static rt_err_t ofw_parse_irq_cells(struct rt_ofw_node *np, int index, struct rt_ofw_cell_args *out_irq_args)
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{
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||
|
|
rt_err_t err;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* interrupts-extended:
|
||
|
|
*
|
||
|
|
* The interrupts-extended property lists the interrupt(s) generated by a
|
||
|
|
* device. interrupts-extended should be used instead of interrupts when a
|
||
|
|
* device is connected to multiple interrupt controllers as it encodes a
|
||
|
|
* parent phandle with each interrupt specifier. Example:
|
||
|
|
*
|
||
|
|
* pic: interrupt-controller@0 {
|
||
|
|
* interrupt-controller;
|
||
|
|
* #interrupt-cells = <1>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* gic: interrupt-controller@1 {
|
||
|
|
* interrupt-controller;
|
||
|
|
* #interrupt-cells = <3>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* node: node {
|
||
|
|
* interrupts-extended = <&pic 9>, <&gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* call `rt_ofw_parse_phandle_cells` to get irq info;
|
||
|
|
*/
|
||
|
|
|
||
|
|
err = rt_ofw_parse_phandle_cells(np, "interrupts-extended", "#interrupt-cells", index, out_irq_args);
|
||
|
|
|
||
|
|
do {
|
||
|
|
int interrupt_cells;
|
||
|
|
const fdt32_t *cell;
|
||
|
|
rt_ssize_t interrupt_len;
|
||
|
|
struct rt_ofw_node *ic_np;
|
||
|
|
|
||
|
|
if (!err)
|
||
|
|
{
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* interrupts (old style):
|
||
|
|
*
|
||
|
|
* The interrupts property of a device node defines the interrupt or
|
||
|
|
* interrupts that are generated by the device. The value of the
|
||
|
|
* interrupts property consists of an arbitrary number of interrupt
|
||
|
|
* specifiers. The format of an interrupt specifier is defined by the
|
||
|
|
* binding of the interrupt domain root.
|
||
|
|
* interrupts is overridden by the interrupts-extended property and
|
||
|
|
* normally only one or the other should be used. Example:
|
||
|
|
*
|
||
|
|
* pic: interrupt-controller@0 {
|
||
|
|
* interrupt-controller;
|
||
|
|
* #interrupt-cells = <1>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* gic: interrupt-controller@1 {
|
||
|
|
* interrupt-controller;
|
||
|
|
* #interrupt-cells = <3>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* node0: node0 {
|
||
|
|
* interrupt-parent = <&pic>;
|
||
|
|
* interrupts = <9>;
|
||
|
|
* };
|
||
|
|
*
|
||
|
|
* node1: node1 {
|
||
|
|
* interrupt-parent = <&gic>;
|
||
|
|
* interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
* };
|
||
|
|
*/
|
||
|
|
|
||
|
|
cell = rt_ofw_prop_read_raw(np, "interrupts", &interrupt_len);
|
||
|
|
|
||
|
|
if (!cell)
|
||
|
|
{
|
||
|
|
err = -RT_ERROR;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
ic_np = rt_ofw_find_irq_parent(np, &interrupt_cells);
|
||
|
|
|
||
|
|
if (!ic_np)
|
||
|
|
{
|
||
|
|
err = -RT_ERROR;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
RT_ASSERT(interrupt_cells <= RT_OFW_MAX_CELL_ARGS);
|
||
|
|
|
||
|
|
if (index >= interrupt_len / (interrupt_cells * sizeof(*cell)))
|
||
|
|
{
|
||
|
|
err = -RT_EINVAL;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
cell += index * interrupt_cells;
|
||
|
|
|
||
|
|
out_irq_args->data = ic_np;
|
||
|
|
out_irq_args->args_count = interrupt_cells;
|
||
|
|
|
||
|
|
for (int idx = 0; idx < interrupt_cells; ++idx, ++cell)
|
||
|
|
{
|
||
|
|
out_irq_args->args[idx] = fdt32_to_cpu(*cell);
|
||
|
|
}
|
||
|
|
|
||
|
|
err = RT_EOK;
|
||
|
|
} while (0);
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_err_t rt_ofw_parse_irq_cells(struct rt_ofw_node *np, int index, struct rt_ofw_cell_args *out_irq_args)
|
||
|
|
{
|
||
|
|
rt_err_t err;
|
||
|
|
|
||
|
|
if (np && index >= 0 && out_irq_args)
|
||
|
|
{
|
||
|
|
err = ofw_parse_irq_cells(np, index, out_irq_args);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
err = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct rt_ofw_node *rt_ofw_find_irq_parent(struct rt_ofw_node *np, int *out_interrupt_cells)
|
||
|
|
{
|
||
|
|
for (np = rt_ofw_node_get(np); np; np = rt_ofw_get_next_parent(np))
|
||
|
|
{
|
||
|
|
rt_phandle ic_phandle;
|
||
|
|
|
||
|
|
if (!rt_ofw_prop_read_u32(np, "interrupt-parent", (rt_uint32_t *)&ic_phandle))
|
||
|
|
{
|
||
|
|
int interrupt_cells;
|
||
|
|
struct rt_ofw_node *ic_np = rt_ofw_find_node_by_phandle(ic_phandle);
|
||
|
|
|
||
|
|
if (ic_np && (interrupt_cells = ofw_interrupt_cells(ic_np)) >= 0)
|
||
|
|
{
|
||
|
|
np = ic_np;
|
||
|
|
|
||
|
|
if (out_interrupt_cells)
|
||
|
|
{
|
||
|
|
*out_interrupt_cells = interrupt_cells;
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_ofw_node_put(ic_np);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return np;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ofw_map_irq(struct rt_ofw_cell_args *irq_args)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
struct rt_ofw_node *ic_np = irq_args->data;
|
||
|
|
struct rt_pic *pic = rt_pic_dynamic_cast(rt_ofw_data(ic_np));
|
||
|
|
|
||
|
|
/* args.data is "interrupt-controller" */
|
||
|
|
if (pic)
|
||
|
|
{
|
||
|
|
struct rt_pic_irq pirq;
|
||
|
|
|
||
|
|
if (!pic->ops->irq_parse)
|
||
|
|
{
|
||
|
|
LOG_E("Master pic MUST implemented irq_parse");
|
||
|
|
RT_ASSERT(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!pic->ops->irq_map)
|
||
|
|
{
|
||
|
|
LOG_E("Master pic MUST implemented irq_map");
|
||
|
|
RT_ASSERT(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
irq = pic->ops->irq_parse(pic, irq_args, &pirq);
|
||
|
|
|
||
|
|
if (!irq)
|
||
|
|
{
|
||
|
|
irq = pic->ops->irq_map(pic, pirq.hwirq, pirq.mode);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("Master pic %s not support", ic_np->full_name);
|
||
|
|
irq = -RT_EIO;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_ofw_node_put(ic_np);
|
||
|
|
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_ofw_map_irq(struct rt_ofw_cell_args *irq_args)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
|
||
|
|
if (irq_args && irq_args->data && irq_args->args_count > 0)
|
||
|
|
{
|
||
|
|
irq = ofw_map_irq(irq_args);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
irq = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_ofw_get_irq_count(struct rt_ofw_node *np)
|
||
|
|
{
|
||
|
|
int count;
|
||
|
|
|
||
|
|
if (np)
|
||
|
|
{
|
||
|
|
struct rt_ofw_cell_args irq_args;
|
||
|
|
|
||
|
|
count = 0;
|
||
|
|
|
||
|
|
while (!ofw_parse_irq_cells(np, count, &irq_args))
|
||
|
|
{
|
||
|
|
++count;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
count = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return count;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_ofw_get_irq(struct rt_ofw_node *np, int index)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
|
||
|
|
if (np && index >= 0)
|
||
|
|
{
|
||
|
|
struct rt_ofw_cell_args irq_args;
|
||
|
|
|
||
|
|
irq = ofw_parse_irq_cells(np, index, &irq_args);
|
||
|
|
|
||
|
|
if (irq >= 0)
|
||
|
|
{
|
||
|
|
rt_phandle cpu_phandle;
|
||
|
|
|
||
|
|
irq = ofw_map_irq(&irq_args);
|
||
|
|
|
||
|
|
if (irq >= 0 && !rt_ofw_prop_read_u32_index(np, "interrupt-affinity", index, &cpu_phandle))
|
||
|
|
{
|
||
|
|
rt_uint64_t cpuid = rt_ofw_get_cpu_id(rt_ofw_find_node_by_phandle(cpu_phandle));
|
||
|
|
|
||
|
|
if ((rt_int64_t)cpuid >= 0)
|
||
|
|
{
|
||
|
|
RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 };
|
||
|
|
|
||
|
|
rt_bitmap_set_bit(affinity, cpuid);
|
||
|
|
|
||
|
|
if (rt_pic_irq_set_affinity(irq, affinity) == -RT_ENOSYS)
|
||
|
|
{
|
||
|
|
LOG_W("%s irq affinity init fail", np->full_name);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
irq = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_ofw_get_irq_by_name(struct rt_ofw_node *np, const char *name)
|
||
|
|
{
|
||
|
|
int irq;
|
||
|
|
|
||
|
|
if (np && name)
|
||
|
|
{
|
||
|
|
int index = rt_ofw_prop_index_of_string(np, "interrupt-names", name);
|
||
|
|
|
||
|
|
if (index >= 0)
|
||
|
|
{
|
||
|
|
irq = rt_ofw_get_irq(np, index);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
irq = -1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
irq = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return irq;
|
||
|
|
}
|