riscv模拟器配置与fpga同步

slab内存分配器似乎不能支持小内存池，改为heap方式

make_riscv.py

@@ -7,7 +7,7 @@ import dataclasses
 from multiprocessing import Process,Queue,Value,cpu_count
 
 
-
+# os.environ["PATH"]="/home/andy/source/my_riscv/bin:"+os.environ["PATH"]
 
 CC="riscv64-unknown-elf-gcc"
 OBJCPY="riscv64-unknown-elf-objcopy"
@@ -24,7 +24,7 @@ CFLAG=[
   "-Wall",
   "-Werror",
   "-g",
-  "-O0",
+  "-Os",
   "-fno-omit-frame-pointer",
   "-msave-restore"
 ]
@@ -244,12 +244,30 @@ def main():
   build_target(SRC)
   os.system(f"{OBJCPY} -O binary {OUTPUT}/{TARGET}.elf {OUTPUT}/{TARGET}.bin")
   os.system(f"{OBJCPY} -O ihex {OUTPUT}/{TARGET}.elf {OUTPUT}/{TARGET}.hex")
-  os.system(f"{OBJDUMP} -d {OUTPUT}/{TARGET}.elf > {OUTPUT}/{TARGET}.lst")
+  os.system(f"{CC} -v > {OUTPUT}/{TARGET}.lst 2>&1")
+  os.system(f"{OBJDUMP} -d {OUTPUT}/{TARGET}.elf >> {OUTPUT}/{TARGET}.lst")
 
 
 
+# 生成fpga的加载文件
+def create_coe_file():
+  with open(f"{OUTPUT}/{TARGET}.bin", mode="rb") as f:
+    data=f.read()
+  data_len=len(data)//4
+  with open(f"{OUTPUT}/{TARGET}.coe", mode='w+') as f:
+    f.write("memory_initialization_radix = 16;\n")
+    f.write("memory_initialization_vector =\n")
+    for index in range(data_len):
+      temp=data[index*4]|(data[index*4+1]<<8)|\
+        (data[index*4+2])<<16|(data[index*4+3]<<24)
+      f.write(f"{temp:08x},\n")
+    for index in range(65536-data_len):
+      f.write(f"{0:08x},\n")
+
+
 if __name__ == "__main__":
   tick_start=time.time()
   main()
+  create_coe_file()
   tick_end=time.time()
   print(f"cost: {tick_end-tick_start}")