118 lines
2.7 KiB
ArmAsm
118 lines
2.7 KiB
ArmAsm
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.equ REGBYTES, 0x4
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.macro PUSH_ALL_REG
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addi sp, sp, -33*REGBYTES
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sw x1, 0*REGBYTES(sp) //ra
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sw x2, 1*REGBYTES(sp) //sp
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sw x3, 2*REGBYTES(sp) //gp
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sw x4, 3*REGBYTES(sp) //tp
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sw x5, 4*REGBYTES(sp) //t0
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sw x6, 5*REGBYTES(sp) //t1
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sw x7, 6*REGBYTES(sp) //t2
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sw x8, 30*REGBYTES(sp)
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sw x9, 8*REGBYTES(sp)
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sw x10, 9*REGBYTES(sp) //a0
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sw x11, 10*REGBYTES(sp) //a1
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sw x12, 11*REGBYTES(sp) //a2
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sw x13, 12*REGBYTES(sp) //a3
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sw x14, 13*REGBYTES(sp) //a4
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sw x15, 14*REGBYTES(sp) //a5
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sw x16, 15*REGBYTES(sp) //a6
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sw x17, 16*REGBYTES(sp) //a7
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sw x18, 17*REGBYTES(sp)
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sw x19, 18*REGBYTES(sp)
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sw x20, 19*REGBYTES(sp)
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sw x21, 20*REGBYTES(sp)
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sw x22, 21*REGBYTES(sp)
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sw x23, 22*REGBYTES(sp)
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sw x24, 23*REGBYTES(sp)
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sw x25, 24*REGBYTES(sp)
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sw x26, 25*REGBYTES(sp)
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sw x27, 26*REGBYTES(sp)
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sw x28, 27*REGBYTES(sp) //t3
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sw x29, 28*REGBYTES(sp) //t4
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sw x30, 29*REGBYTES(sp) //t5
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sw x31, 7*REGBYTES(sp) //t6
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csrr t0, mstatus
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sw t0, 31*REGBYTES(sp)
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csrr t0, mepc
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sw t0, 32*REGBYTES(sp)
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.endm
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.macro POP_ALL_REG
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lw t0, 31* REGBYTES(sp)
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csrw mstatus, t0
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lw t0, 32 * REGBYTES(sp)
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csrw mepc, t0
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lw x1, 0*REGBYTES(sp) //ra
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lw x5, 4*REGBYTES(sp)
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lw x6, 5*REGBYTES(sp)
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lw x7, 6*REGBYTES(sp)
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lw x8, 30*REGBYTES(sp)
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lw x9, 8*REGBYTES(sp)
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lw x10, 9*REGBYTES(sp)
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lw x11, 10*REGBYTES(sp)
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lw x12, 11*REGBYTES(sp)
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lw x13, 12*REGBYTES(sp)
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lw x14, 13*REGBYTES(sp)
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lw x15, 14*REGBYTES(sp)
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lw x16, 15*REGBYTES(sp)
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lw x17, 16*REGBYTES(sp)
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lw x18, 17*REGBYTES(sp)
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lw x19, 18*REGBYTES(sp)
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lw x20, 19*REGBYTES(sp)
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lw x21, 20*REGBYTES(sp)
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lw x22, 21*REGBYTES(sp)
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lw x23, 22*REGBYTES(sp)
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lw x24, 23*REGBYTES(sp)
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lw x25, 24*REGBYTES(sp)
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lw x26, 25*REGBYTES(sp)
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lw x27, 26*REGBYTES(sp)
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lw x28, 27*REGBYTES(sp)
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lw x29, 28*REGBYTES(sp)
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lw x30, 29*REGBYTES(sp)
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lw x31, 7*REGBYTES(sp)
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addi sp, sp, 33*REGBYTES
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.endm
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# .section .interrupt.text
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.extern trap_entry
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.global _trap_entry
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.align 4
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_trap_entry:
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csrw mscratch, sp
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mv a1, sp
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la sp, _exc_sp
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call trap_entry
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csrr sp, mscratch
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POP_ALL_REG
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mret
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# .section .interrupt.text
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.extern trap_entry
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.extern interrupt_entry
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.global trap_handler
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.equ TRAP_INTERRUPT_MODE_MASK, 0x80000000
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.align 4
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trap_handler:
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PUSH_ALL_REG
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csrr a0, mcause
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li a1, TRAP_INTERRUPT_MODE_MASK
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li a2, 0x000000ff
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and a1, a0, a1
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and a0, a2, a0
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beqz a1, _trap_entry
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csrw mscratch, sp
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la sp, _irq_sp
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call interrupt_entry
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csrr sp, mscratch
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POP_ALL_REG
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mret
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