131 lines
5.3 KiB
C
Executable File
131 lines
5.3 KiB
C
Executable File
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-07-25 weety first version
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*/
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#ifndef __CMD_H__
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#define __CMD_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* class 1 */
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#define GO_IDLE_STATE 0 /* bc */
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#define SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
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#define ALL_SEND_CID 2 /* bcr R2 */
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#define SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
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#define SET_DSR 4 /* bc [31:16] RCA */
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#define SWITCH 6 /* ac [31:0] See below R1b */
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#define SELECT_CARD 7 /* ac [31:16] RCA R1 */
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#define SEND_EXT_CSD 8 /* adtc R1 */
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#define SEND_CSD 9 /* ac [31:16] RCA R2 */
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#define SEND_CID 10 /* ac [31:16] RCA R2 */
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#define READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
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#define STOP_TRANSMISSION 12 /* ac R1b */
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#define SEND_STATUS 13 /* ac [31:16] RCA R1 */
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#define GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
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#define SPI_READ_OCR 58 /* spi spi_R3 */
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#define SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
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/* class 2 */
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#define SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
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#define READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
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#define READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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#define SEND_TUNING_BLOCK 19 /* adtc R1 */
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#define SEND_TUNING_BLOCK_HS200 21 /* adtc R1*/
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/* class 3 */
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#define WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
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/* class 4 */
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#define SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
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#define WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
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#define WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
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#define PROGRAM_CID 26 /* adtc R1 */
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#define PROGRAM_CSD 27 /* adtc R1 */
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/* class 6 */
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#define SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
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#define CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
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#define SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
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/* class 5 */
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#define ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
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#define ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
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#define ERASE 38 /* ac R1b */
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/* class 9 */
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#define FAST_IO 39 /* ac <Complex> R4 */
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#define GO_IRQ_STATE 40 /* bcr R5 */
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/* class 7 */
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#define LOCK_UNLOCK 42 /* adtc R1b */
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/* class 8 */
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#define APP_CMD 55 /* ac [31:16] RCA R1 */
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#define GEN_CMD 56 /* adtc [0] RD/WR R1 */
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/* SD commands type argument response */
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/* class 0 */
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/* This is basically the same command as for MMC with some quirks. */
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#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
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#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
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/* class 10 */
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#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
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/* Application commands */
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#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
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#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
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#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
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#define SD_APP_SEND_SCR 51 /* adtc R1 */
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#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
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#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
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#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */
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/* SDIO commands type argument response */
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#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
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#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
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#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
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/* CMD52 arguments */
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#define SDIO_ARG_CMD52_READ (0<<31)
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#define SDIO_ARG_CMD52_WRITE (1u<<31)
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#define SDIO_ARG_CMD52_FUNC_SHIFT 28
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#define SDIO_ARG_CMD52_FUNC_MASK 0x7
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#define SDIO_ARG_CMD52_RAW_FLAG (1u<<27)
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#define SDIO_ARG_CMD52_REG_SHIFT 9
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#define SDIO_ARG_CMD52_REG_MASK 0x1ffff
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#define SDIO_ARG_CMD52_DATA_SHIFT 0
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#define SDIO_ARG_CMD52_DATA_MASK 0xff
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#define SDIO_R5_DATA(resp) ((resp)[0] & 0xff)
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/* CMD53 arguments */
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#define SDIO_ARG_CMD53_READ (0<<31)
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#define SDIO_ARG_CMD53_WRITE (1u<<31)
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#define SDIO_ARG_CMD53_FUNC_SHIFT 28
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#define SDIO_ARG_CMD53_FUNC_MASK 0x7
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#define SDIO_ARG_CMD53_BLOCK_MODE (1u<<27)
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#define SDIO_ARG_CMD53_INCREMENT (1u<<26)
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#define SDIO_ARG_CMD53_REG_SHIFT 9
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#define SDIO_ARG_CMD53_REG_MASK 0x1ffff
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#define SDIO_ARG_CMD53_LENGTH_SHIFT 0
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#define SDIO_ARG_CMD53_LENGTH_MASK 0x1ff
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#define SDIO_ARG_CMD53_LENGTH_MAX 511
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#ifdef __cplusplus
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}
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#endif
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#endif
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