274 lines
11 KiB
C
274 lines
11 KiB
C
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/*
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* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* CMSIS-Core(M) MPU API for Armv7-M MPU
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*/
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#ifndef ARM_MPU_ARMV7_H
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#define ARM_MPU_ARMV7_H
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
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#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
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#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
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#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
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#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
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#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
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#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
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#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
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#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
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#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
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#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
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#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
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#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
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#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
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#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
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#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
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#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
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#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
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#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
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#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
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#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
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#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
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#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
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#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
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#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
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#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
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#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
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#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
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#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
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#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
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#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
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#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
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#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
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#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
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/** MPU Region Base Address Register Value
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*
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* \param Region The region to be configured, number 0 to 15.
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* \param BaseAddress The base address for the region.
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*/
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#define ARM_MPU_RBAR(Region, BaseAddress) \
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(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
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((Region) & MPU_RBAR_REGION_Msk) | \
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(MPU_RBAR_VALID_Msk))
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/**
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* MPU Memory Access Attributes
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*
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* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
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* \param IsShareable Region is shareable between multiple bus masters.
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* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
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* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
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*/
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#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
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((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
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(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
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(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
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(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
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/**
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* MPU Region Attribute and Size Register Value
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*
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* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
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* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
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* \param SubRegionDisable Sub-region disable field.
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* \param Size Region size of the region to be configured, for example 4K, 8K.
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*/
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#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
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((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
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(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
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(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
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(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
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(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
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(((MPU_RASR_ENABLE_Msk))))
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/**
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* MPU Region Attribute and Size Register Value
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*
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* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
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* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
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* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
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* \param IsShareable Region is shareable between multiple bus masters.
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* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
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* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
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* \param SubRegionDisable Sub-region disable field.
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* \param Size Region size of the region to be configured, for example 4K, 8K.
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*/
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#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
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ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
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/**
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* MPU Memory Access Attribute for strongly ordered memory.
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* - TEX: 000b
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* - Shareable
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* - Non-cacheable
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* - Non-bufferable
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*/
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#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
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/**
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* MPU Memory Access Attribute for device memory.
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* - TEX: 000b (if shareable) or 010b (if non-shareable)
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* - Shareable or non-shareable
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* - Non-cacheable
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* - Bufferable (if shareable) or non-bufferable (if non-shareable)
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*
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* \param IsShareable Configures the device memory as shareable or non-shareable.
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*/
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#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
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/**
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* MPU Memory Access Attribute for normal memory.
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* - TEX: 1BBb (reflecting outer cacheability rules)
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* - Shareable or non-shareable
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* - Cacheable or non-cacheable (reflecting inner cacheability rules)
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* - Bufferable or non-bufferable (reflecting inner cacheability rules)
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*
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* \param OuterCp Configures the outer cache policy.
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* \param InnerCp Configures the inner cache policy.
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* \param IsShareable Configures the memory as shareable or non-shareable.
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*/
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#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
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/**
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* MPU Memory Access Attribute non-cacheable policy.
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*/
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#define ARM_MPU_CACHEP_NOCACHE 0U
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/**
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* MPU Memory Access Attribute write-back, write and read allocate policy.
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*/
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#define ARM_MPU_CACHEP_WB_WRA 1U
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/**
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* MPU Memory Access Attribute write-through, no write allocate policy.
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*/
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#define ARM_MPU_CACHEP_WT_NWA 2U
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/**
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* MPU Memory Access Attribute write-back, no write allocate policy.
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*/
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#define ARM_MPU_CACHEP_WB_NWA 3U
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/**
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* Struct for a single MPU Region
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*/
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typedef struct {
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uint32_t RBAR; //!< The region base address register value (RBAR)
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uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
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} ARM_MPU_Region_t;
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/** Enable the MPU.
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* \param MPU_Control Default access permissions for unconfigured regions.
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*/
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__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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{
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__DMB();
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MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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__DSB();
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__ISB();
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}
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/** Disable the MPU.
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*/
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__STATIC_INLINE void ARM_MPU_Disable(void)
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{
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__DMB();
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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__DSB();
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__ISB();
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}
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/** Clear and disable the given MPU region.
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* \param rnr Region number to be cleared.
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*/
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__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
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{
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MPU->RNR = rnr;
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MPU->RASR = 0U;
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}
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/** Configure an MPU region.
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* \param rbar Value for RBAR register.
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* \param rasr Value for RASR register.
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*/
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__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
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{
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MPU->RBAR = rbar;
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MPU->RASR = rasr;
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}
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/** Configure the given MPU region.
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* \param rnr Region number to be configured.
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* \param rbar Value for RBAR register.
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* \param rasr Value for RASR register.
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*/
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__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
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{
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MPU->RNR = rnr;
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MPU->RBAR = rbar;
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MPU->RASR = rasr;
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}
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/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
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* \param dst Destination data is copied to.
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* \param src Source data is copied from.
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* \param len Amount of data words to be copied.
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*/
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__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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{
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uint32_t i;
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for (i = 0U; i < len; ++i)
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{
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dst[i] = src[i];
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}
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}
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/** Load the given number of MPU regions from a table.
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* \param table Pointer to the MPU configuration table.
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* \param cnt Amount of regions to be configured.
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*/
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__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
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{
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const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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while (cnt > MPU_TYPE_RALIASES) {
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ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
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table += MPU_TYPE_RALIASES;
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cnt -= MPU_TYPE_RALIASES;
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}
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ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
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}
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#endif
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