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source/main/system_stm32mp1xx.c
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290
source/main/system_stm32mp1xx.c
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/**
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******************************************************************************
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* @file system_stm32mp1xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32mp1xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock frequency, it can
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* be used by the user application to setup
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* the SysTick timer or configure other
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* parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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*
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32mp1xx_system
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* @{
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*/
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/** @addtogroup STM32MP1xx_System_Private_Includes
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* @{
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*/
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#include "stm32mp1xx_hal.h"
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM mounted
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on EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) each time HAL_RCC_ClockConfig() is called to configure the system clock
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frequency
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Note: If you use this function to configure the system clock;
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then there is no need to call the first functions listed above,
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since SystemCoreClock variable is updated automatically.
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*/
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uint32_t SystemCoreClock = HSI_VALUE;
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32MP1xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if defined (CORE_CM4)
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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#if defined (VECT_TAB_SRAM)
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SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#endif
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/* Disable all interrupts and events */
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CLEAR_REG(EXTI_C2->IMR1);
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CLEAR_REG(EXTI_C2->IMR2);
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CLEAR_REG(EXTI_C2->IMR3);
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CLEAR_REG(EXTI_C2->EMR1);
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CLEAR_REG(EXTI_C2->EMR2);
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CLEAR_REG(EXTI_C2->EMR3);
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#else
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#error Please #define CORE_CM4
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock frequency (Hz),
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* it can be used by the user application to setup the SysTick timer or
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* configure other parameters.
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*
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* @note Each time the core clock changes, this function must be called to
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* update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the
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* HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the
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* HSE_VALUE(**)
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*
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* - If SYSCLK source is CSI, SystemCoreClock will contain the
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* CSI_VALUE(***)
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*
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* - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
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* HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
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* multiplied/divided by the PLL3 factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
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* (default value 64 MHz) but the real value may vary depending
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* on the variations in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
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* (default value 24 MHz), user has to ensure that HSE_VALUE is
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* same as the real frequency of the crystal used. Otherwise, this
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* function may have wrong result.
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*
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* (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
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* (default value 4 MHz)but the real value may vary depending
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* on the variations in voltage and temperature.
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*
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* - The result of this function could be not correct when using
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* fractional value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t pllsource, pll3m, pll3fracen;
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float fracn1, pll3vco;
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switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
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break;
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case 0x01: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x02: /* CSI used as system clock source */
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SystemCoreClock = CSI_VALUE;
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break;
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case 0x03: /* PLL3_P used as system clock source */
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pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
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pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
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pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
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fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
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pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1/(float) 0x1FFFU));
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if (pll3m != 0U)
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{
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switch (pllsource)
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{
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case 0x00: /* HSI used as PLL clock source */
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pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
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break;
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case 0x01: /* HSE used as PLL clock source */
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pll3vco *= (float)(HSE_VALUE / pll3m);
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break;
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case 0x02: /* CSI used as PLL clock source */
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pll3vco *= (float)(CSI_VALUE / pll3m);
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break;
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case 0x03: /* No clock source for PLL */
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pll3vco = 0;
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break;
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}
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SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
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}
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else
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{
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SystemCoreClock = 0U;
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}
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break;
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}
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/* Compute mcu_ck */
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SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
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}
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#ifdef DATA_IN_ExtSRAM
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32L4xx.s before jump to main.
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* This function configures the external SRAM mounted on Eval boards
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* This SRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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}
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#endif /* DATA_IN_ExtSRAM */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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