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建立工程，成功创建两个虚拟串口

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ranchuan
2023-06-21 18:00:56 +08:00
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/**
******************************************************************************
* @file stm32mp1xx.h
* @author MCD Application Team
* @brief CMSIS STM32MP1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32MP1xx device used in the target application
* - To use or not the peripheral<61>s drivers in application code(i.e.
* code will be based on direct access to peripheral<61>s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32mp1xx
* @{
*/
#ifndef __STM32MP1xx_H
#define __STM32MP1xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/* Uncomment the line below according to the target STM32MP1 device used in your
application
*/
#if !defined (STM32MP1)
#define STM32MP1
#endif /* STM32MP1 */
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number
*/
#define __STM32MP1xx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32MP1xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32MP1xx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32MP1xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32MP1xx_CMSIS_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(CORE_CM4)
#if defined(STM32MP15xx) /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
#include "stm32mp157cxx_cm4.h"
#elif defined(STM32MP157Axx)
#include "stm32mp157axx_cm4.h"
#elif defined(STM32MP157Cxx)
#include "stm32mp157cxx_cm4.h"
#elif defined(STM32MP157Dxx)
#include "stm32mp157dxx_cm4.h"
#elif defined(STM32MP157Fxx)
#include "stm32mp157fxx_cm4.h"
#elif defined(STM32MP153Axx)
#include "stm32mp153axx_cm4.h"
#elif defined(STM32MP153Cxx)
#include "stm32mp153cxx_cm4.h"
#elif defined(STM32MP153Dxx)
#include "stm32mp153dxx_cm4.h"
#elif defined(STM32MP153Fxx)
#include "stm32mp153fxx_cm4.h"
#elif defined(STM32MP151Axx)
#include "stm32mp151axx_cm4.h"
#elif defined(STM32MP151Cxx)
#include "stm32mp151cxx_cm4.h"
#elif defined(STM32MP151Dxx)
#include "stm32mp151dxx_cm4.h"
#elif defined(STM32MP151Fxx)
#include "stm32mp151fxx_cm4.h"
#else
#error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
#endif
#endif
#if defined(CORE_CA7)
#if defined(STM32MP15xx) /* keep for backward compatibility STM32MP15xx = STM32MP157Cxx */
#include "stm32mp157cxx_ca7.h"
#elif defined(STM32MP157Axx)
#include "stm32mp157axx_ca7.h"
#elif defined(STM32MP157Cxx)
#include "stm32mp157cxx_ca7.h"
#elif defined(STM32MP157Dxx)
#include "stm32mp157dxx_ca7.h"
#elif defined(STM32MP157Fxx)
#include "stm32mp157fxx_ca7.h"
#elif defined(STM32MP153Axx)
#include "stm32mp153axx_ca7.h"
#elif defined(STM32MP153Cxx)
#include "stm32mp153cxx_ca7.h"
#elif defined(STM32MP153Dxx)
#include "stm32mp153dxx_ca7.h"
#elif defined(STM32MP153Fxx)
#include "stm32mp153fxx_ca7.h"
#elif defined(STM32MP151Axx)
#include "stm32mp151axx_ca7.h"
#elif defined(STM32MP151Cxx)
#include "stm32mp151cxx_ca7.h"
#elif defined(STM32MP151Dxx)
#include "stm32mp151dxx_ca7.h"
#elif defined(STM32MP151Fxx)
#include "stm32mp151fxx_ca7.h"
#else
#error "Please select first the target STM32MP1xx device used in your application (in stm32mp1xx.h file)"
#endif
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32mp1xx_hal_conf.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32MP1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32mp1xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32mp1xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32MP1XX_H
#define __SYSTEM_STM32MP1XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32MP1xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Core1 Clock Frequency */
extern uint32_t SystemCore1Clock; /*!< System Core1 Clock Frequency */
extern uint32_t SystemCore2Clock; /*!< System Core2 Clock Frequency */
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32MP1XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<!DOCTYPE html>
<html><head>
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><title>Release Notes for STM32MP1xx CMSIS</title>
<style>
div.Section1 {
page: Section1;
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}
h1 {
font-size: 24pt;
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}
ul {
font-family: Arial,Helvetica,sans-serif;
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}
caption {
margin-top: 10px;
font-family: Arial,Helvetica,sans-serif;
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}
hr {
width: 100%;
}
.guidance {
background-color: #e5b8b7;
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}
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font-style: normal;
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}
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}
.tickets th {
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}
.tickets td {
border: 1pt solid #9cc2e5;
min-height: 32px;
}
tr:nth-child(even) {background-color: #cee2f2;}
tr:nth-child(even) {background-color: #e8f1f9;}
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}
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margin-top: 3px;
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}
.topic3 {
margin-top: 3px;
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margin-left: 20px;
}
#purpose {
margin-top: 3px;
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}
#identification {
margin-top: 3px;
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}
</style></head>
<body link="blue" vlink="blue">
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}</script><a href="../../../../../Release_Notes.html">Back to Release page</a>
<div style="width: 1034px;" class="Section1">
<div id="header">
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for<o:p></o:p> STM32MP1xx CMSIS Device</span></h1>
<p style="text-align: center;">Copyright 2019
STMicroelectronics</p>
<p style="text-align: center;"><img style="width: 104px; height: 77px;" id="st_logo" alt="&lt;ST logo&gt; image" src="../../../../../_htmresc/st_logo.png"></p>
</div>
<div id="license" class="topic1">
<h2>License</h2>
<p>This software component is licensed by ST under BSD 3-Clause
license, the "License"; You may not use this component except in
compliance with the License. You may obtain a copy of the License at:</p>
<p style="text-align: center; color: white;"><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank">https://opensource.org/licenses/BSD-3-Clause</a><a href="https://opensource.org/licenses/BSD-3-Clause" target="_blank"><span style="background-color: yellow;"></span></a></p>
</div>
<div id="release_container" class="topic1">
<div class="topic2" id="identification">
<h3 style="width: 230px;">V1.2.0 / 03-Feb-2020</h3>
</div>
<div style="margin-left: 20px; width: 974px;" class="topic3" id="changes">
<h4>Main changes</h4>
<ul><li>Header files:&nbsp;</li><ul><li>Add new Part Number for 800MHz</li><li>Update license with BSD 3-Clause template</li><li>Rework CMSIS for RTC/TAMP, GPIO and TIM</li><li>Rename TIM Break source bit definition</li></ul></ul><ul><li>Update Linker Template&nbsp;file for KEIL and IAR:</li><ul><li>Add OpenAMP region ( region present by default, to comment if needed )</li></ul></ul><br>
</div>
<div class="topic3" id="contents">
<h4>Contents</h4>
<ul>
<li>CMSIS devices files for:</li><ul><li>STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">151D</span>xx ,STM32MP<span style="font-weight: bold;">151F</span>xx</li><li>STM32MP<span style="font-weight: bold;">153C</span>xx ,STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">153D</span>xx ,STM32MP<span style="font-weight: bold;">153F</span>xx</li><li>STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx, STM32MP<span style="font-weight: bold;">157D</span>xx ,STM32MP<span style="font-weight: bold;">157F</span>xx</li></ul></ul><ul>
</ul>
</div>
</div>
<div style="margin-left: 40px;"><button id="filter_hist" onclick="toggle_history()">Show
History</button><br>
</div>
<div id="history" class="topic1" hidden="">
<h2>Update History</h2>
<br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-Sept-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
<h4>Main changes</h4>
<ul><li>Header files:&nbsp;</li><ul><li>Update FMC bit definition</li><li>Update ETH&nbsp;bit definition</li><li>update EXTI_EXTICR&nbsp;bit definition</li><li>Update I2C&nbsp;bit definition</li><li>Update SPI&nbsp;bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, SPI_I2SCFGR)&nbsp;</li><li>TMPSENS IP renamed DTS</li><li>Update FDCAN TXBC&nbsp;bit definition</li><li>Update DAC_DHR8RD&nbsp;bit definition</li><li>Add CRYP in STM32MP151Cx and STM32MP153Cx</li><li>Update TIM / LPTIM&nbsp;bit definition + add missing macros</li></ul><li>Update system_stm32mp1xx.c</li><ul><li>Update SystemCoreClock</li></ul><li>Update startup file for KEIL and IAR</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
<h4>Contents</h4>
<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
<br>
</div><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 22-January-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
<h4>Main changes</h4>
<ul><li>First official release for <span style="font-weight: bold;">STM32MP15xx</span> devices<br>
</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
<h4>Contents</h4>
<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
<br>
</div><br><br>
</div>
<div id="product_doc" class="topic1">
<hr>
<p style="text-align: center;">For complete
documentation on&nbsp;<span style="background-color: white;">STM32
Microcontrollers</span>, visit: <span style="background-color: white;"><a href="http://www.st.com/STM32" target="_blank">www.st.com/STM32</a></span></p>
</div>
</div>
</body></html>

27
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/linker/stm32mp15xx_m4.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description ***
; *************************************************************
LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
.isr_vector +0 {
startup*.o (RESET, +First)
}
}
LR_IROM1 0x10000000 0x00020000 { ; load region size_region
ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x10020000 0x00020000 { ; RW data
.ANY (+RW +ZI)
}
; ***** Create region for OPENAMP *****
; *** These 4 lines can be commented if OPENAMP is not used ***
.resource_table +0 ALIGN 4 { ; resource table
*(.resource_table)
}
__OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
}

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;******************************************************************************
;* File Name : startup_stm32mp15xx.s
;* Author : MCD Application Team
;* Description : STM32MP15xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD WWDG1_IRQHandler ;
DCD PVD_AVD_IRQHandler ;
DCD TAMP_IRQHandler ;
DCD RTC_WKUP_ALARM_IRQHandler ;
DCD RESERVED4_IRQHandler ;
DCD RCC_IRQHandler ;
DCD EXTI0_IRQHandler ;
DCD EXTI1_IRQHandler ;
DCD EXTI2_IRQHandler ;
DCD EXTI3_IRQHandler ;
DCD EXTI4_IRQHandler ;
DCD DMA1_Stream0_IRQHandler ;
DCD DMA1_Stream1_IRQHandler ;
DCD DMA1_Stream2_IRQHandler ;
DCD DMA1_Stream3_IRQHandler ;
DCD DMA1_Stream4_IRQHandler ;
DCD DMA1_Stream5_IRQHandler ;
DCD DMA1_Stream6_IRQHandler ;
DCD ADC1_IRQHandler ;
DCD FDCAN1_IT0_IRQHandler ;
DCD FDCAN2_IT0_IRQHandler ;
DCD FDCAN1_IT1_IRQHandler ;
DCD FDCAN2_IT1_IRQHandler ;
DCD EXTI5_IRQHandler ;
DCD TIM1_BRK_IRQHandler ;
DCD TIM1_UP_IRQHandler ;
DCD TIM1_TRG_COM_IRQHandler ;
DCD TIM1_CC_IRQHandler ;
DCD TIM2_IRQHandler ;
DCD TIM3_IRQHandler ;
DCD TIM4_IRQHandler ;
DCD I2C1_EV_IRQHandler ;
DCD I2C1_ER_IRQHandler ;
DCD I2C2_EV_IRQHandler ;
DCD I2C2_ER_IRQHandler ;
DCD SPI1_IRQHandler ;
DCD SPI2_IRQHandler ;
DCD USART1_IRQHandler ;
DCD USART2_IRQHandler ;
DCD USART3_IRQHandler ;
DCD EXTI10_IRQHandler ;
DCD RTC_TIMESTAMP_IRQHandler ;
DCD EXTI11_IRQHandler ;
DCD TIM8_BRK_IRQHandler ;
DCD TIM8_UP_IRQHandler ;
DCD TIM8_TRG_COM_IRQHandler ;
DCD TIM8_CC_IRQHandler ;
DCD DMA1_Stream7_IRQHandler ;
DCD FMC_IRQHandler ;
DCD SDMMC1_IRQHandler ;
DCD TIM5_IRQHandler ;
DCD SPI3_IRQHandler ;
DCD UART4_IRQHandler ;
DCD UART5_IRQHandler ;
DCD TIM6_IRQHandler ;
DCD TIM7_IRQHandler ;
DCD DMA2_Stream0_IRQHandler ;
DCD DMA2_Stream1_IRQHandler ;
DCD DMA2_Stream2_IRQHandler ;
DCD DMA2_Stream3_IRQHandler ;
DCD DMA2_Stream4_IRQHandler ;
DCD ETH1_IRQHandler ;
DCD ETH1_WKUP_IRQHandler ;
DCD FDCAN_CAL_IRQHandler ;
DCD EXTI6_IRQHandler ;
DCD EXTI7_IRQHandler ;
DCD EXTI8_IRQHandler ;
DCD EXTI9_IRQHandler ;
DCD DMA2_Stream5_IRQHandler ;
DCD DMA2_Stream6_IRQHandler ;
DCD DMA2_Stream7_IRQHandler ;
DCD USART6_IRQHandler ;
DCD I2C3_EV_IRQHandler ;
DCD I2C3_ER_IRQHandler ;
DCD USBH_OHCI_IRQHandler ;
DCD USBH_EHCI_IRQHandler ;
DCD EXTI12_IRQHandler ;
DCD EXTI13_IRQHandler ;
DCD DCMI_IRQHandler ;
DCD CRYP1_IRQHandler ;
DCD HASH1_IRQHandler ;
DCD FPU_IRQHandler ;
DCD UART7_IRQHandler ;
DCD UART8_IRQHandler ;
DCD SPI4_IRQHandler ;
DCD SPI5_IRQHandler ;
DCD SPI6_IRQHandler ;
DCD SAI1_IRQHandler ;
DCD LTDC_IRQHandler ;
DCD LTDC_ER_IRQHandler ;
DCD ADC2_IRQHandler ;
DCD SAI2_IRQHandler ;
DCD QUADSPI_IRQHandler ;
DCD LPTIM1_IRQHandler ;
DCD CEC_IRQHandler ;
DCD I2C4_EV_IRQHandler ;
DCD I2C4_ER_IRQHandler ;
DCD SPDIF_RX_IRQHandler ;
DCD OTG_IRQHandler ;
DCD RESERVED99_IRQHandler ;
DCD IPCC_RX0_IRQHandler ;
DCD IPCC_TX0_IRQHandler ;
DCD DMAMUX1_OVR_IRQHandler ;
DCD IPCC_RX1_IRQHandler ;
DCD IPCC_TX1_IRQHandler ;
DCD CRYP2_IRQHandler ;
DCD HASH2_IRQHandler ;
DCD I2C5_EV_IRQHandler ;
DCD I2C5_ER_IRQHandler ;
DCD GPU_IRQHandler ;
DCD DFSDM1_FLT0_IRQHandler ;
DCD DFSDM1_FLT1_IRQHandler ;
DCD DFSDM1_FLT2_IRQHandler ;
DCD DFSDM1_FLT3_IRQHandler ;
DCD SAI3_IRQHandler ;
DCD DFSDM1_FLT4_IRQHandler ;
DCD TIM15_IRQHandler ;
DCD TIM16_IRQHandler ;
DCD TIM17_IRQHandler ;
DCD TIM12_IRQHandler ;
DCD MDIOS_IRQHandler ;
DCD EXTI14_IRQHandler ;
DCD MDMA_IRQHandler ;
DCD DSI_IRQHandler ;
DCD SDMMC2_IRQHandler ;
DCD HSEM_IT2_IRQHandler ;
DCD DFSDM1_FLT5_IRQHandler ;
DCD EXTI15_IRQHandler ;
DCD nCTIIRQ1_IRQHandler ;
DCD nCTIIRQ2_IRQHandler ;
DCD TIM13_IRQHandler ;
DCD TIM14_IRQHandler ;
DCD DAC_IRQHandler ;
DCD RNG1_IRQHandler ;
DCD RNG2_IRQHandler ;
DCD I2C6_EV_IRQHandler ;
DCD I2C6_ER_IRQHandler ;
DCD SDMMC3_IRQHandler ;
DCD LPTIM2_IRQHandler ;
DCD LPTIM3_IRQHandler ;
DCD LPTIM4_IRQHandler ;
DCD LPTIM5_IRQHandler ;
DCD ETH1_LPI_IRQHandler ;
DCD RESERVED143_IRQHandler ;
DCD MPU_SEV_IRQHandler ;
DCD RCC_WAKEUP_IRQHandler ;
DCD SAI4_IRQHandler ;
DCD DTS_IRQHandler ;
DCD RESERVED148_IRQHandler ;
DCD WAKEUP_PIN_IRQHandler ;
SPACE (73 * 4) ; Interrupts 151 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler WWDG1_IRQHandler ; Window WatchDog 1
Set_Default_Handler PVD_AVD_IRQHandler ; PVD and AVD through EXTI Line detection
Set_Default_Handler TAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
Set_Default_Handler RTC_WKUP_ALARM_IRQHandler ; RTC Wakeup and Alarm through the EXTI line
Set_Default_Handler RESERVED4_IRQHandler ; Reserved
Set_Default_Handler RCC_IRQHandler ; RCC
Set_Default_Handler EXTI0_IRQHandler ; EXTI Line0
Set_Default_Handler EXTI1_IRQHandler ; EXTI Line1
Set_Default_Handler EXTI2_IRQHandler ; EXTI Line2
Set_Default_Handler EXTI3_IRQHandler ; EXTI Line3
Set_Default_Handler EXTI4_IRQHandler ; EXTI Line4
Set_Default_Handler DMA1_Stream0_IRQHandler ; DMA1 Stream 0
Set_Default_Handler DMA1_Stream1_IRQHandler ; DMA1 Stream 1
Set_Default_Handler DMA1_Stream2_IRQHandler ; DMA1 Stream 2
Set_Default_Handler DMA1_Stream3_IRQHandler ; DMA1 Stream 3
Set_Default_Handler DMA1_Stream4_IRQHandler ; DMA1 Stream 4
Set_Default_Handler DMA1_Stream5_IRQHandler ; DMA1 Stream 5
Set_Default_Handler DMA1_Stream6_IRQHandler ; DMA1 Stream 6
Set_Default_Handler ADC1_IRQHandler ; ADC1
Set_Default_Handler FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt line 0
Set_Default_Handler FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt line 0
Set_Default_Handler FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt line 1
Set_Default_Handler FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt line 1
Set_Default_Handler EXTI5_IRQHandler ; External Line5 interrupts through AIEC
Set_Default_Handler TIM1_BRK_IRQHandler ; TIM1 Break interrupt
Set_Default_Handler TIM1_UP_IRQHandler ; TIM1 Update Interrupt
Set_Default_Handler TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
Set_Default_Handler TIM1_CC_IRQHandler ; TIM1 Capture Compare
Set_Default_Handler TIM2_IRQHandler ; TIM2
Set_Default_Handler TIM3_IRQHandler ; TIM3
Set_Default_Handler TIM4_IRQHandler ; TIM4
Set_Default_Handler I2C1_EV_IRQHandler ; I2C1 Event
Set_Default_Handler I2C1_ER_IRQHandler ; I2C1 Error
Set_Default_Handler I2C2_EV_IRQHandler ; I2C2 Event
Set_Default_Handler I2C2_ER_IRQHandler ; I2C2 Error
Set_Default_Handler SPI1_IRQHandler ; SPI1
Set_Default_Handler SPI2_IRQHandler ; SPI2
Set_Default_Handler USART1_IRQHandler ; USART1
Set_Default_Handler USART2_IRQHandler ; USART2
Set_Default_Handler USART3_IRQHandler ; USART3
Set_Default_Handler EXTI10_IRQHandler ; External Line10 interrupts through AIEC
Set_Default_Handler RTC_TIMESTAMP_IRQHandler ; RTC TimeStamp through EXTI Line
Set_Default_Handler EXTI11_IRQHandler ; External Line11 interrupts through AIEC
Set_Default_Handler TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
Set_Default_Handler TIM8_UP_IRQHandler ; TIM8 Update Interrupt
Set_Default_Handler TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
Set_Default_Handler TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
Set_Default_Handler DMA1_Stream7_IRQHandler ; DMA1 Stream7
Set_Default_Handler FMC_IRQHandler ; FMC
Set_Default_Handler SDMMC1_IRQHandler ; SDMMC1
Set_Default_Handler TIM5_IRQHandler ; TIM5
Set_Default_Handler SPI3_IRQHandler ; SPI3
Set_Default_Handler UART4_IRQHandler ; UART4
Set_Default_Handler UART5_IRQHandler ; UART5
Set_Default_Handler TIM6_IRQHandler ; TIM6
Set_Default_Handler TIM7_IRQHandler ; TIM7
Set_Default_Handler DMA2_Stream0_IRQHandler ; DMA2 Stream 0
Set_Default_Handler DMA2_Stream1_IRQHandler ; DMA2 Stream 1
Set_Default_Handler DMA2_Stream2_IRQHandler ; DMA2 Stream 2
Set_Default_Handler DMA2_Stream3_IRQHandler ; DMA2 Stream 3
Set_Default_Handler DMA2_Stream4_IRQHandler ; DMA2 Stream 4
Set_Default_Handler ETH1_IRQHandler ; Ethernet
Set_Default_Handler ETH1_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
Set_Default_Handler FDCAN_CAL_IRQHandler ; FDCAN Calibration
Set_Default_Handler EXTI6_IRQHandler ; EXTI Line6 interrupts through AIEC
Set_Default_Handler EXTI7_IRQHandler ; EXTI Line7 interrupts through AIEC
Set_Default_Handler EXTI8_IRQHandler ; EXTI Line8 interrupts through AIEC
Set_Default_Handler EXTI9_IRQHandler ; EXTI Line9 interrupts through AIEC
Set_Default_Handler DMA2_Stream5_IRQHandler ; DMA2 Stream 5
Set_Default_Handler DMA2_Stream6_IRQHandler ; DMA2 Stream 6
Set_Default_Handler DMA2_Stream7_IRQHandler ; DMA2 Stream 7
Set_Default_Handler USART6_IRQHandler ; USART6
Set_Default_Handler I2C3_EV_IRQHandler ; I2C3 event
Set_Default_Handler I2C3_ER_IRQHandler ; I2C3 error
Set_Default_Handler USBH_OHCI_IRQHandler ; USB Host OHCI
Set_Default_Handler USBH_EHCI_IRQHandler ; USB Host EHCI
Set_Default_Handler EXTI12_IRQHandler ; EXTI Line12 interrupts through AIEC
Set_Default_Handler EXTI13_IRQHandler ; EXTI Line13 interrupts through AIEC
Set_Default_Handler DCMI_IRQHandler ; DCMI
Set_Default_Handler CRYP1_IRQHandler ; Crypto1 global interrupt
Set_Default_Handler HASH1_IRQHandler ; Crypto Hash1 interrupt
Set_Default_Handler FPU_IRQHandler ; FPU
Set_Default_Handler UART7_IRQHandler ; UART7
Set_Default_Handler UART8_IRQHandler ; UART8
Set_Default_Handler SPI4_IRQHandler ; SPI4
Set_Default_Handler SPI5_IRQHandler ; SPI5
Set_Default_Handler SPI6_IRQHandler ; SPI6
Set_Default_Handler SAI1_IRQHandler ; SAI1
Set_Default_Handler LTDC_IRQHandler ; LTDC
Set_Default_Handler LTDC_ER_IRQHandler ; LTDC error
Set_Default_Handler ADC2_IRQHandler ; ADC2
Set_Default_Handler SAI2_IRQHandler ; SAI2
Set_Default_Handler QUADSPI_IRQHandler ; QUADSPI
Set_Default_Handler LPTIM1_IRQHandler ; LPTIM1 global interrupt
Set_Default_Handler CEC_IRQHandler ; HDMI_CEC
Set_Default_Handler I2C4_EV_IRQHandler ; I2C4 Event
Set_Default_Handler I2C4_ER_IRQHandler ; I2C4 Error
Set_Default_Handler SPDIF_RX_IRQHandler ; SPDIF_RX
Set_Default_Handler OTG_IRQHandler ; USB On The Go HS global interrupt
Set_Default_Handler RESERVED99_IRQHandler ; Reserved
Set_Default_Handler IPCC_RX0_IRQHandler ; Mailbox RX0 Free interrupt
Set_Default_Handler IPCC_TX0_IRQHandler ; Mailbox TX0 Free interrupt
Set_Default_Handler DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
Set_Default_Handler IPCC_RX1_IRQHandler ; Mailbox RX1 Free interrupt
Set_Default_Handler IPCC_TX1_IRQHandler ; Mailbox TX1 Free interrupt
Set_Default_Handler CRYP2_IRQHandler ; Crypto2 global interrupt
Set_Default_Handler HASH2_IRQHandler ; Crypto Hash2 interrupt
Set_Default_Handler I2C5_EV_IRQHandler ; I2C5 Event Interrupt
Set_Default_Handler I2C5_ER_IRQHandler ; I2C5 Error Interrupt
Set_Default_Handler GPU_IRQHandler ; GPU Global Interrupt
Set_Default_Handler DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
Set_Default_Handler DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
Set_Default_Handler DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
Set_Default_Handler DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
Set_Default_Handler SAI3_IRQHandler ; SAI3 global Interrupt
Set_Default_Handler DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
Set_Default_Handler TIM15_IRQHandler ; TIM15 global Interrupt
Set_Default_Handler TIM16_IRQHandler ; TIM16 global Interrupt
Set_Default_Handler TIM17_IRQHandler ; TIM17 global Interrupt
Set_Default_Handler TIM12_IRQHandler ; TIM12 global Interrupt
Set_Default_Handler MDIOS_IRQHandler ; MDIOS global Interrupt
Set_Default_Handler EXTI14_IRQHandler ; EXTI Line14 interrupts through AIEC
Set_Default_Handler MDMA_IRQHandler ; MDMA global Interrupt
Set_Default_Handler DSI_IRQHandler ; DSI global Interrupt
Set_Default_Handler SDMMC2_IRQHandler ; SDMMC2 global Interrupt
Set_Default_Handler HSEM_IT2_IRQHandler ; HSEM global Interrupt
Set_Default_Handler DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
Set_Default_Handler EXTI15_IRQHandler ; EXTI Line15 interrupts through AIEC
Set_Default_Handler nCTIIRQ1_IRQHandler ; Cortex-M4 CTI interrupt 1
Set_Default_Handler nCTIIRQ2_IRQHandler ; Cortex-M4 CTI interrupt 2
Set_Default_Handler TIM13_IRQHandler ; TIM13 global interrupt
Set_Default_Handler TIM14_IRQHandler ; TIM14 global interrupt
Set_Default_Handler DAC_IRQHandler ; DAC1 and DAC2 underrun error interrupts
Set_Default_Handler RNG1_IRQHandler ; RNG1 interrupt
Set_Default_Handler RNG2_IRQHandler ; RNG2 interrupt
Set_Default_Handler I2C6_EV_IRQHandler ; I2C6 Event Interrupt
Set_Default_Handler I2C6_ER_IRQHandler ; I2C6 Error Interrupt
Set_Default_Handler SDMMC3_IRQHandler ; SDMMC3 global Interrupt
Set_Default_Handler LPTIM2_IRQHandler ; LPTIM2 global interrupt
Set_Default_Handler LPTIM3_IRQHandler ; LPTIM3 global interrupt
Set_Default_Handler LPTIM4_IRQHandler ; LPTIM4 global interrupt
Set_Default_Handler LPTIM5_IRQHandler ; LPTIM5 global interrupt
Set_Default_Handler ETH1_LPI_IRQHandler ; Reserved
Set_Default_Handler RESERVED143_IRQHandler ; Reserved
Set_Default_Handler MPU_SEV_IRQHandler ; MPU Send Event through AIEC
Set_Default_Handler RCC_WAKEUP_IRQHandler ; RCC Wake up interrupt
Set_Default_Handler SAI4_IRQHandler ; SAI4 global interrupt
Set_Default_Handler DTS_IRQHandler ; Temperature sensor interrupt
Set_Default_Handler RESERVED148_IRQHandler ; Reserved
Set_Default_Handler WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

202
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/linker/stm32mp15xx_m4.ld Normal file
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/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Abstract : Linker script for STM32MP1 series
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
** All rights reserved.</center></h2>
**
** This software component is licensed by ST under BSD 3-Clause license,
** the License; You may not use this file except in compliance with the
** License. You may obtain a copy of the License at:
** opensource.org/licenses/BSD-3-Clause
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x10040000; /* end of RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Memories definition */
MEMORY
{
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000298
m_text (RX) : ORIGIN = 0x10000000, LENGTH = 0x00020000
m_data (RW) : ORIGIN = 0x10020000, LENGTH = 0x00020000
m_ipc_shm (RW) : ORIGIN = 0x10040000, LENGTH = 0x00008000
}
/* Symbols needed for OpenAMP to enable rpmsg */
__OPENAMP_region_start__ = ORIGIN(m_ipc_shm);
__OPENAMP_region_end__ = ORIGIN(m_ipc_shm)+LENGTH(m_ipc_shm);
/* Sections */
SECTIONS
{
/* The startup code into ROM memory */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data into ROM memory */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} > m_text
/* Constant data into ROM memory*/
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} > m_text
.ARM.extab : {
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} > m_text
.ARM : {
. = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(4);
} > m_text
.preinit_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} > m_text
.init_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} > m_text
.fini_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} > m_text
/* Used by the startup to initialize data */
__DATA_ROM = .;
_sidata = LOADADDR(.data);
/* Initialized data sections */
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} > m_data
__DATA_END = __DATA_ROM + (_edata - _sdata);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
.resource_table :
{
. = ALIGN(4);
KEEP (*(.resource_table*))
. = ALIGN(4);
} > m_data
/* Uninitialized data section into RAM memory */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} > m_data
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} > m_data
/* Remove information from the compiler libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

792
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s Normal file
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/**
******************************************************************************
* @file startup_stm32mp15xx.s
* @author MCD Application Team
* @brief STM32MP15xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .startup_copro_fw.Reset_Handler,"ax"
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _sidata: End of code section, i.e., begin of data sections to copy from.
* _sdata/_edata: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
// ldr r0, =SystemInit
// blx r0
/* Call static constructors */
bl __libc_init_array
// ldr r0, =__libc_init_array
// blx r0
/* Call the application's entry point.*/
bl main
//ldr r0, =main
//blx r0
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack // Top of Stack
.word Reset_Handler // Reset Handler
.word NMI_Handler // NMI Handler
.word HardFault_Handler // Hard Fault Handler
.word MemManage_Handler // MPU Fault Handler
.word BusFault_Handler // Bus Fault Handler
.word UsageFault_Handler // Usage Fault Handler
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word 0 // Reserved
.word SVC_Handler // SVCall Handler
.word DebugMon_Handler // Debug Monitor Handler
.word 0 // Reserved
.word PendSV_Handler // PendSV Handler
.word SysTick_Handler // SysTick Handler
// External Interrupts
.word WWDG1_IRQHandler // Window WatchDog 1
.word PVD_AVD_IRQHandler // PVD and AVD through EXTI Line detection
.word TAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
.word RTC_WKUP_ALARM_IRQHandler // RTC Wakeup and Alarm through the EXTI line
.word RESERVED4_IRQHandler // Reserved
.word RCC_IRQHandler // RCC
.word EXTI0_IRQHandler // EXTI Line0
.word EXTI1_IRQHandler // EXTI Line1
.word EXTI2_IRQHandler // EXTI Line2
.word EXTI3_IRQHandler // EXTI Line3
.word EXTI4_IRQHandler // EXTI Line4
.word DMA1_Stream0_IRQHandler // DMA1 Stream 0
.word DMA1_Stream1_IRQHandler // DMA1 Stream 1
.word DMA1_Stream2_IRQHandler // DMA1 Stream 2
.word DMA1_Stream3_IRQHandler // DMA1 Stream 3
.word DMA1_Stream4_IRQHandler // DMA1 Stream 4
.word DMA1_Stream5_IRQHandler // DMA1 Stream 5
.word DMA1_Stream6_IRQHandler // DMA1 Stream 6
.word ADC1_IRQHandler // ADC1
.word FDCAN1_IT0_IRQHandler // FDCAN1 Interrupt line 0
.word FDCAN2_IT0_IRQHandler // FDCAN2 Interrupt line 0
.word FDCAN1_IT1_IRQHandler // FDCAN1 Interrupt line 1
.word FDCAN2_IT1_IRQHandler // FDCAN2 Interrupt line 1
.word EXTI5_IRQHandler // External Line5 interrupts through AIEC
.word TIM1_BRK_IRQHandler // TIM1 Break interrupt
.word TIM1_UP_IRQHandler // TIM1 Update Interrupt
.word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation Interrupt
.word TIM1_CC_IRQHandler // TIM1 Capture Compare
.word TIM2_IRQHandler // TIM2
.word TIM3_IRQHandler // TIM3
.word TIM4_IRQHandler // TIM4
.word I2C1_EV_IRQHandler // I2C1 Event
.word I2C1_ER_IRQHandler // I2C1 Error
.word I2C2_EV_IRQHandler // I2C2 Event
.word I2C2_ER_IRQHandler // I2C2 Error
.word SPI1_IRQHandler // SPI1
.word SPI2_IRQHandler // SPI2
.word USART1_IRQHandler // USART1
.word USART2_IRQHandler // USART2
.word USART3_IRQHandler // USART3
.word EXTI10_IRQHandler // External Line10 interrupts through AIEC
.word RTC_TIMESTAMP_IRQHandler // RTC TimeStamp through EXTI Line
.word EXTI11_IRQHandler // External Line11 interrupts through AIEC
.word TIM8_BRK_IRQHandler // TIM8 Break Interrupt
.word TIM8_UP_IRQHandler // TIM8 Update Interrupt
.word TIM8_TRG_COM_IRQHandler // TIM8 Trigger and Commutation Interrupt
.word TIM8_CC_IRQHandler // TIM8 Capture Compare Interrupt
.word DMA1_Stream7_IRQHandler // DMA1 Stream7
.word FMC_IRQHandler // FMC
.word SDMMC1_IRQHandler // SDMMC1
.word TIM5_IRQHandler // TIM5
.word SPI3_IRQHandler // SPI3
.word UART4_IRQHandler // UART4
.word UART5_IRQHandler // UART5
.word TIM6_IRQHandler // TIM6
.word TIM7_IRQHandler // TIM7
.word DMA2_Stream0_IRQHandler // DMA2 Stream 0
.word DMA2_Stream1_IRQHandler // DMA2 Stream 1
.word DMA2_Stream2_IRQHandler // DMA2 Stream 2
.word DMA2_Stream3_IRQHandler // DMA2 Stream 3
.word DMA2_Stream4_IRQHandler // DMA2 Stream 4
.word ETH1_IRQHandler // Ethernet
.word ETH1_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
.word FDCAN_CAL_IRQHandler // FDCAN Calibration
.word EXTI6_IRQHandler // EXTI Line6 interrupts through AIEC
.word EXTI7_IRQHandler // EXTI Line7 interrupts through AIEC
.word EXTI8_IRQHandler // EXTI Line8 interrupts through AIEC
.word EXTI9_IRQHandler // EXTI Line9 interrupts through AIEC
.word DMA2_Stream5_IRQHandler // DMA2 Stream 5
.word DMA2_Stream6_IRQHandler // DMA2 Stream 6
.word DMA2_Stream7_IRQHandler // DMA2 Stream 7
.word USART6_IRQHandler // USART6
.word I2C3_EV_IRQHandler // I2C3 event
.word I2C3_ER_IRQHandler // I2C3 error
.word USBH_OHCI_IRQHandler // USB Host OHCI
.word USBH_EHCI_IRQHandler // USB Host EHCI
.word EXTI12_IRQHandler // EXTI Line12 interrupts through AIEC
.word EXTI13_IRQHandler // EXTI Line13 interrupts through AIEC
.word DCMI_IRQHandler // DCMI
.word CRYP1_IRQHandler // Crypto1 global interrupt
.word HASH1_IRQHandler // Crypto Hash1 interrupt
.word FPU_IRQHandler // FPU
.word UART7_IRQHandler // UART7
.word UART8_IRQHandler // UART8
.word SPI4_IRQHandler // SPI4
.word SPI5_IRQHandler // SPI5
.word SPI6_IRQHandler // SPI6
.word SAI1_IRQHandler // SAI1
.word LTDC_IRQHandler // LTDC
.word LTDC_ER_IRQHandler // LTDC error
.word ADC2_IRQHandler // ADC2
.word SAI2_IRQHandler // SAI2
.word QUADSPI_IRQHandler // QUADSPI
.word LPTIM1_IRQHandler // LPTIM1 global interrupt
.word CEC_IRQHandler // HDMI_CEC
.word I2C4_EV_IRQHandler // I2C4 Event
.word I2C4_ER_IRQHandler // I2C4 Error
.word SPDIF_RX_IRQHandler // SPDIF_RX
.word OTG_IRQHandler // USB On The Go HS global interrupt
.word RESERVED99_IRQHandler // Reserved
.word IPCC_RX0_IRQHandler // Mailbox RX0 Free interrupt
.word IPCC_TX0_IRQHandler // Mailbox TX0 Free interrupt
.word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt
.word IPCC_RX1_IRQHandler // Mailbox RX1 Free interrupt
.word IPCC_TX1_IRQHandler // Mailbox TX1 Free interrupt
.word CRYP2_IRQHandler // Crypto2 global interrupt
.word HASH2_IRQHandler // Crypto Hash2 interrupt
.word I2C5_EV_IRQHandler // I2C5 Event Interrupt
.word I2C5_ER_IRQHandler // I2C5 Error Interrupt
.word GPU_IRQHandler // GPU Global Interrupt
.word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt
.word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt
.word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt
.word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt
.word SAI3_IRQHandler // SAI3 global Interrupt
.word DFSDM1_FLT4_IRQHandler // DFSDM Filter4 Interrupt
.word TIM15_IRQHandler // TIM15 global Interrupt
.word TIM16_IRQHandler // TIM16 global Interrupt
.word TIM17_IRQHandler // TIM17 global Interrupt
.word TIM12_IRQHandler // TIM12 global Interrupt
.word MDIOS_IRQHandler // MDIOS global Interrupt
.word EXTI14_IRQHandler // EXTI Line14 interrupts through AIEC
.word MDMA_IRQHandler // MDMA global Interrupt
.word DSI_IRQHandler // DSI global Interrupt
.word SDMMC2_IRQHandler // SDMMC2 global Interrupt
.word HSEM_IT2_IRQHandler // HSEM global Interrupt
.word DFSDM1_FLT5_IRQHandler // DFSDM Filter5 Interrupt
.word EXTI15_IRQHandler // EXTI Line15 interrupts through AIEC
.word nCTIIRQ1_IRQHandler // Cortex-M4 CTI interrupt 1
.word nCTIIRQ2_IRQHandler // Cortex-M4 CTI interrupt 2
.word TIM13_IRQHandler // TIM13 global interrupt
.word TIM14_IRQHandler // TIM14 global interrupt
.word DAC_IRQHandler // DAC1 and DAC2 underrun error interrupts
.word RNG1_IRQHandler // RNG1 interrupt
.word RNG2_IRQHandler // RNG2 interrupt
.word I2C6_EV_IRQHandler // I2C6 Event Interrupt
.word I2C6_ER_IRQHandler // I2C6 Error Interrupt
.word SDMMC3_IRQHandler // SDMMC3 global Interrupt
.word LPTIM2_IRQHandler // LPTIM2 global interrupt
.word LPTIM3_IRQHandler // LPTIM3 global interrupt
.word LPTIM4_IRQHandler // LPTIM4 global interrupt
.word LPTIM5_IRQHandler // LPTIM5 global interrupt
.word ETH1_LPI_IRQHandler // ETH1_LPI interrupt
.word RESERVED143_IRQHandler // Reserved
.word MPU_SEV_IRQHandler // MPU Send Event through AIEC
.word RCC_WAKEUP_IRQHandler // RCC Wake up interrupt
.word SAI4_IRQHandler // SAI4 global interrupt
.word DTS_IRQHandler // Temperature sensor interrupt
.word RESERVED148_IRQHandler // Reserved
.word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak RESERVED4_IRQHandler
.thumb_set RESERVED4_IRQHandler,Default_Handler
.weak RESERVED99_IRQHandler
.thumb_set RESERVED99_IRQHandler,Default_Handler
.weak ETH1_LPI_IRQHandler
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
.weak RESERVED143_IRQHandler
.thumb_set RESERVED143_IRQHandler,Default_Handler
.weak WWDG1_IRQHandler
.thumb_set WWDG1_IRQHandler,Default_Handler
.weak PVD_AVD_IRQHandler
.thumb_set PVD_AVD_IRQHandler,Default_Handler
.weak TAMP_IRQHandler
.thumb_set TAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_ALARM_IRQHandler
.thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak EXTI5_IRQHandler
.thumb_set EXTI5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI10_IRQHandler
.thumb_set EXTI10_IRQHandler,Default_Handler
.weak RTC_TIMESTAMP_IRQHandler
.thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
.weak EXTI11_IRQHandler
.thumb_set EXTI11_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH1_IRQHandler
.thumb_set ETH1_IRQHandler,Default_Handler
.weak ETH1_WKUP_IRQHandler
.thumb_set ETH1_WKUP_IRQHandler,Default_Handler
.weak ETH1_LPI_IRQHandler
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
.weak EXTI6_IRQHandler
.thumb_set EXTI6_IRQHandler,Default_Handler
.weak EXTI7_IRQHandler
.thumb_set EXTI7_IRQHandler,Default_Handler
.weak EXTI8_IRQHandler
.thumb_set EXTI8_IRQHandler,Default_Handler
.weak EXTI9_IRQHandler
.thumb_set EXTI9_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak USBH_OHCI_IRQHandler
.thumb_set USBH_OHCI_IRQHandler,Default_Handler
.weak USBH_EHCI_IRQHandler
.thumb_set USBH_EHCI_IRQHandler,Default_Handler
.weak EXTI12_IRQHandler
.thumb_set EXTI12_IRQHandler,Default_Handler
.weak EXTI13_IRQHandler
.thumb_set EXTI13_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CRYP1_IRQHandler
.thumb_set CRYP1_IRQHandler,Default_Handler
.weak HASH1_IRQHandler
.thumb_set HASH1_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak OTG_IRQHandler
.thumb_set OTG_IRQHandler,Default_Handler
.weak IPCC_RX0_IRQHandler
.thumb_set IPCC_RX0_IRQHandler,Default_Handler
.weak IPCC_TX0_IRQHandler
.thumb_set IPCC_TX0_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak IPCC_RX1_IRQHandler
.thumb_set IPCC_RX1_IRQHandler,Default_Handler
.weak IPCC_TX1_IRQHandler
.thumb_set IPCC_TX1_IRQHandler,Default_Handler
.weak CRYP2_IRQHandler
.thumb_set CRYP2_IRQHandler,Default_Handler
.weak HASH2_IRQHandler
.thumb_set HASH2_IRQHandler,Default_Handler
.weak I2C5_EV_IRQHandler
.thumb_set I2C5_EV_IRQHandler,Default_Handler
.weak I2C5_ER_IRQHandler
.thumb_set I2C5_ER_IRQHandler,Default_Handler
.weak GPU_IRQHandler
.thumb_set GPU_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SAI3_IRQHandler
.thumb_set SAI3_IRQHandler,Default_Handler
.weak DFSDM1_FLT4_IRQHandler
.thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak TIM12_IRQHandler
.thumb_set TIM12_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak EXTI14_IRQHandler
.thumb_set EXTI14_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak DSI_IRQHandler
.thumb_set DSI_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM_IT2_IRQHandler
.thumb_set HSEM_IT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT5_IRQHandler
.thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
.weak EXTI15_IRQHandler
.thumb_set EXTI15_IRQHandler,Default_Handler
.weak nCTIIRQ1_IRQHandler
.thumb_set nCTIIRQ1_IRQHandler,Default_Handler
.weak nCTIIRQ2_IRQHandler
.thumb_set nCTIIRQ2_IRQHandler,Default_Handler
.weak TIM13_IRQHandler
.thumb_set TIM13_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak DAC_IRQHandler
.thumb_set DAC_IRQHandler,Default_Handler
.weak RNG1_IRQHandler
.thumb_set RNG1_IRQHandler,Default_Handler
.weak RNG2_IRQHandler
.thumb_set RNG2_IRQHandler,Default_Handler
.weak I2C6_EV_IRQHandler
.thumb_set I2C6_EV_IRQHandler,Default_Handler
.weak I2C6_ER_IRQHandler
.thumb_set I2C6_ER_IRQHandler,Default_Handler
.weak SDMMC3_IRQHandler
.thumb_set SDMMC3_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak MPU_SEV_IRQHandler
.thumb_set MPU_SEV_IRQHandler,Default_Handler
.weak RCC_WAKEUP_IRQHandler
.thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
.weak SAI4_IRQHandler
.thumb_set SAI4_IRQHandler,Default_Handler
.weak DTS_IRQHandler
.thumb_set DTS_IRQHandler,Default_Handler
.weak RESERVED148_IRQHandler
.thumb_set RESERVED148_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

40
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_retram.icf Normal file
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@@ -0,0 +1,40 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_text_start__ = 0x00000000;
define symbol __ICFEDIT_region_text_end__ = 0x00008000;
define symbol __ICFEDIT_region_data_start__ = 0x00008000;
define symbol __ICFEDIT_region_data_end__ = 0x00010000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region text_region = mem:[from __ICFEDIT_region_text_start__ to __ICFEDIT_region_text_end__];
define region data_region = mem:[from __ICFEDIT_region_data_start__ to __ICFEDIT_region_data_end__];
keep { section .resource_table };
".resource_table" : place in data_region {section .resource_table};
/* Create region for OPENAMP */
/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
define symbol __OPENAMP_region_start__ = 0x10040000;
define symbol __OPENAMP_region_size__ = 0x8000;
export symbol __OPENAMP_region_start__;
export symbol __OPENAMP_region_size__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit};
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in text_region { readonly };
place in data_region { readwrite,
block CSTACK, block HEAP};

40
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/linker/stm32mp15xx_sram.icf Normal file
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@@ -0,0 +1,40 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_text_start__ = 0x10000000;
define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF;
define symbol __ICFEDIT_region_data_start__ = 0x10020000;
define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region text_region = mem:[from __ICFEDIT_region_text_start__ to __ICFEDIT_region_text_end__];
define region data_region = mem:[from __ICFEDIT_region_data_start__ to __ICFEDIT_region_data_end__];
keep { section .resource_table };
".resource_table" : place in data_region {section .resource_table};
/* Create region for OPENAMP */
/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
define symbol __OPENAMP_region_start__ = 0x10040000;
define symbol __OPENAMP_region_size__ = 0x8000;
export symbol __OPENAMP_region_start__;
export symbol __OPENAMP_region_size__;
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit};
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in text_region { readonly };
place in data_region { readwrite,
block CSTACK, block HEAP};

1009
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/iar/startup_stm32mp15xx.s Normal file
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File diff suppressed because it is too large Load Diff

290
source/stm32lib/CMSIS/Device/ST/STM32MP1xx/Source/Templates/system_stm32mp1xx.c Normal file
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@@ -0,0 +1,290 @@
/**
******************************************************************************
* @file system_stm32mp1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32mp1xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock frequency, it can
* be used by the user application to setup
* the SysTick timer or configure other
* parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
*
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32mp1xx_system
* @{
*/
/** @addtogroup STM32MP1xx_System_Private_Includes
* @{
*/
#include "stm32mp1xx_hal.h"
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x400. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) each time HAL_RCC_ClockConfig() is called to configure the system clock
frequency
Note: If you use this function to configure the system clock;
then there is no need to call the first functions listed above,
since SystemCoreClock variable is updated automatically.
*/
uint32_t SystemCoreClock = HSI_VALUE;
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
#if defined (CORE_CM4)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Configure the Vector Table location add offset address ------------------*/
#if defined (VECT_TAB_SRAM)
SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif
/* Disable all interrupts and events */
CLEAR_REG(EXTI_C2->IMR1);
CLEAR_REG(EXTI_C2->IMR2);
CLEAR_REG(EXTI_C2->IMR3);
CLEAR_REG(EXTI_C2->EMR1);
CLEAR_REG(EXTI_C2->EMR2);
CLEAR_REG(EXTI_C2->EMR3);
#else
#error Please #define CORE_CM4
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock frequency (Hz),
* it can be used by the user application to setup the SysTick timer or
* configure other parameters.
*
* @note Each time the core clock changes, this function must be called to
* update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the
* HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the
* HSE_VALUE(**)
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the
* CSI_VALUE(***)
*
* - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
* HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
* multiplied/divided by the PLL3 factors.
*
* (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 64 MHz) but the real value may vary depending
* on the variations in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 24 MHz), user has to ensure that HSE_VALUE is
* same as the real frequency of the crystal used. Otherwise, this
* function may have wrong result.
*
* (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 4 MHz)but the real value may vary depending
* on the variations in voltage and temperature.
*
* - The result of this function could be not correct when using
* fractional value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllsource, pll3m, pll3fracen;
float fracn1, pll3vco;
switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
break;
case 0x01: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x02: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case 0x03: /* PLL3_P used as system clock source */
pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF));
if (pll3m != 0U)
{
switch (pllsource)
{
case 0x00: /* HSI used as PLL clock source */
pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
break;
case 0x01: /* HSE used as PLL clock source */
pll3vco *= (float)(HSE_VALUE / pll3m);
break;
case 0x02: /* CSI used as PLL clock source */
pll3vco *= (float)(CSI_VALUE / pll3m);
break;
case 0x03: /* No clock source for PLL */
pll3vco = 0;
break;
}
SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
}
else
{
SystemCoreClock = 0U;
}
break;
}
/* Compute mcu_ck */
SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
}
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32mp15xx.s before jump to main.
* This function configures the external SRAM mounted on Eval boards
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/