建立工程，成功创建两个虚拟串口
This commit is contained in:
ranchuan
@@ -0,0 +1,27 @@
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; *************************************************************
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; *** Scatter-Loading Description ***
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; *************************************************************
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LR_VECTORS 0x00000000 0x00000400 { ; load region size_region
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.isr_vector +0 {
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startup*.o (RESET, +First)
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}
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}
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LR_IROM1 0x10000000 0x00020000 { ; load region size_region
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ER_IROM1 0x10000000 0x00020000 { ; load address = execution address
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*(InRoot$$Sections)
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.ANY (+RO)
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.ANY (+XO)
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}
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RW_IRAM1 0x10020000 0x00020000 { ; RW data
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.ANY (+RW +ZI)
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}
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; ***** Create region for OPENAMP *****
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; *** These 4 lines can be commented if OPENAMP is not used ***
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.resource_table +0 ALIGN 4 { ; resource table
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*(.resource_table)
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}
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__OpenAMP_SHMEM__ 0x10040000 EMPTY 0x8000 {} ; Shared Memory area used by OpenAMP
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}
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@@ -0,0 +1,439 @@
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;******************************************************************************
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;* File Name : startup_stm32mp15xx.s
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;* Author : MCD Application Team
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;* Description : STM32MP15xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM4 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;******************************************************************************
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;* @attention
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;*
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;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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;* All rights reserved.</center></h2>
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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__stack_limit
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; -14 NMI Handler
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DCD HardFault_Handler ; -13 Hard Fault Handler
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DCD MemManage_Handler ; -12 MPU Fault Handler
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DCD BusFault_Handler ; -11 Bus Fault Handler
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DCD UsageFault_Handler ; -10 Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; -5 SVCall Handler
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DCD DebugMon_Handler ; -4 Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; -2 PendSV Handler
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DCD SysTick_Handler ; -1 SysTick Handler
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; Interrupts
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DCD WWDG1_IRQHandler ;
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DCD PVD_AVD_IRQHandler ;
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DCD TAMP_IRQHandler ;
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DCD RTC_WKUP_ALARM_IRQHandler ;
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DCD RESERVED4_IRQHandler ;
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DCD RCC_IRQHandler ;
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DCD EXTI0_IRQHandler ;
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DCD EXTI1_IRQHandler ;
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DCD EXTI2_IRQHandler ;
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DCD EXTI3_IRQHandler ;
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DCD EXTI4_IRQHandler ;
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DCD DMA1_Stream0_IRQHandler ;
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DCD DMA1_Stream1_IRQHandler ;
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DCD DMA1_Stream2_IRQHandler ;
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DCD DMA1_Stream3_IRQHandler ;
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DCD DMA1_Stream4_IRQHandler ;
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DCD DMA1_Stream5_IRQHandler ;
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DCD DMA1_Stream6_IRQHandler ;
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DCD ADC1_IRQHandler ;
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DCD FDCAN1_IT0_IRQHandler ;
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DCD FDCAN2_IT0_IRQHandler ;
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DCD FDCAN1_IT1_IRQHandler ;
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DCD FDCAN2_IT1_IRQHandler ;
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DCD EXTI5_IRQHandler ;
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DCD TIM1_BRK_IRQHandler ;
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DCD TIM1_UP_IRQHandler ;
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DCD TIM1_TRG_COM_IRQHandler ;
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DCD TIM1_CC_IRQHandler ;
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DCD TIM2_IRQHandler ;
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DCD TIM3_IRQHandler ;
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DCD TIM4_IRQHandler ;
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DCD I2C1_EV_IRQHandler ;
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DCD I2C1_ER_IRQHandler ;
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DCD I2C2_EV_IRQHandler ;
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DCD I2C2_ER_IRQHandler ;
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DCD SPI1_IRQHandler ;
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DCD SPI2_IRQHandler ;
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DCD USART1_IRQHandler ;
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DCD USART2_IRQHandler ;
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DCD USART3_IRQHandler ;
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DCD EXTI10_IRQHandler ;
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DCD RTC_TIMESTAMP_IRQHandler ;
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DCD EXTI11_IRQHandler ;
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DCD TIM8_BRK_IRQHandler ;
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DCD TIM8_UP_IRQHandler ;
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DCD TIM8_TRG_COM_IRQHandler ;
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DCD TIM8_CC_IRQHandler ;
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DCD DMA1_Stream7_IRQHandler ;
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DCD FMC_IRQHandler ;
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DCD SDMMC1_IRQHandler ;
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DCD TIM5_IRQHandler ;
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DCD SPI3_IRQHandler ;
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DCD UART4_IRQHandler ;
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DCD UART5_IRQHandler ;
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DCD TIM6_IRQHandler ;
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DCD TIM7_IRQHandler ;
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DCD DMA2_Stream0_IRQHandler ;
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DCD DMA2_Stream1_IRQHandler ;
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DCD DMA2_Stream2_IRQHandler ;
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DCD DMA2_Stream3_IRQHandler ;
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DCD DMA2_Stream4_IRQHandler ;
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DCD ETH1_IRQHandler ;
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DCD ETH1_WKUP_IRQHandler ;
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DCD FDCAN_CAL_IRQHandler ;
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DCD EXTI6_IRQHandler ;
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DCD EXTI7_IRQHandler ;
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DCD EXTI8_IRQHandler ;
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DCD EXTI9_IRQHandler ;
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DCD DMA2_Stream5_IRQHandler ;
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DCD DMA2_Stream6_IRQHandler ;
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DCD DMA2_Stream7_IRQHandler ;
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DCD USART6_IRQHandler ;
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DCD I2C3_EV_IRQHandler ;
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DCD I2C3_ER_IRQHandler ;
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DCD USBH_OHCI_IRQHandler ;
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DCD USBH_EHCI_IRQHandler ;
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DCD EXTI12_IRQHandler ;
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DCD EXTI13_IRQHandler ;
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DCD DCMI_IRQHandler ;
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DCD CRYP1_IRQHandler ;
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DCD HASH1_IRQHandler ;
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DCD FPU_IRQHandler ;
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DCD UART7_IRQHandler ;
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DCD UART8_IRQHandler ;
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DCD SPI4_IRQHandler ;
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DCD SPI5_IRQHandler ;
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DCD SPI6_IRQHandler ;
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DCD SAI1_IRQHandler ;
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DCD LTDC_IRQHandler ;
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DCD LTDC_ER_IRQHandler ;
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DCD ADC2_IRQHandler ;
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DCD SAI2_IRQHandler ;
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DCD QUADSPI_IRQHandler ;
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DCD LPTIM1_IRQHandler ;
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DCD CEC_IRQHandler ;
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DCD I2C4_EV_IRQHandler ;
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DCD I2C4_ER_IRQHandler ;
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DCD SPDIF_RX_IRQHandler ;
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DCD OTG_IRQHandler ;
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DCD RESERVED99_IRQHandler ;
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DCD IPCC_RX0_IRQHandler ;
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DCD IPCC_TX0_IRQHandler ;
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DCD DMAMUX1_OVR_IRQHandler ;
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DCD IPCC_RX1_IRQHandler ;
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DCD IPCC_TX1_IRQHandler ;
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DCD CRYP2_IRQHandler ;
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DCD HASH2_IRQHandler ;
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DCD I2C5_EV_IRQHandler ;
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DCD I2C5_ER_IRQHandler ;
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DCD GPU_IRQHandler ;
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DCD DFSDM1_FLT0_IRQHandler ;
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DCD DFSDM1_FLT1_IRQHandler ;
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DCD DFSDM1_FLT2_IRQHandler ;
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DCD DFSDM1_FLT3_IRQHandler ;
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DCD SAI3_IRQHandler ;
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DCD DFSDM1_FLT4_IRQHandler ;
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DCD TIM15_IRQHandler ;
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DCD TIM16_IRQHandler ;
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DCD TIM17_IRQHandler ;
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DCD TIM12_IRQHandler ;
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DCD MDIOS_IRQHandler ;
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DCD EXTI14_IRQHandler ;
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DCD MDMA_IRQHandler ;
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DCD DSI_IRQHandler ;
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DCD SDMMC2_IRQHandler ;
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DCD HSEM_IT2_IRQHandler ;
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DCD DFSDM1_FLT5_IRQHandler ;
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DCD EXTI15_IRQHandler ;
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DCD nCTIIRQ1_IRQHandler ;
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DCD nCTIIRQ2_IRQHandler ;
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DCD TIM13_IRQHandler ;
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DCD TIM14_IRQHandler ;
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DCD DAC_IRQHandler ;
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DCD RNG1_IRQHandler ;
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DCD RNG2_IRQHandler ;
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DCD I2C6_EV_IRQHandler ;
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DCD I2C6_ER_IRQHandler ;
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DCD SDMMC3_IRQHandler ;
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DCD LPTIM2_IRQHandler ;
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DCD LPTIM3_IRQHandler ;
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DCD LPTIM4_IRQHandler ;
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DCD LPTIM5_IRQHandler ;
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DCD ETH1_LPI_IRQHandler ;
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DCD RESERVED143_IRQHandler ;
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DCD MPU_SEV_IRQHandler ;
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DCD RCC_WAKEUP_IRQHandler ;
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DCD SAI4_IRQHandler ;
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DCD DTS_IRQHandler ;
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DCD RESERVED148_IRQHandler ;
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DCD WAKEUP_PIN_IRQHandler ;
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SPACE (73 * 4) ; Interrupts 151 .. 224 are left out
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Macro to define default exception/interrupt handlers.
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; Default handler are weak symbols with an endless loop.
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; They can be overwritten by real handlers.
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MACRO
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Set_Default_Handler $Handler_Name
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$Handler_Name PROC
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EXPORT $Handler_Name [WEAK]
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B .
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ENDP
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MEND
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; Default exception/interrupt handler
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Set_Default_Handler NMI_Handler
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Set_Default_Handler HardFault_Handler
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Set_Default_Handler MemManage_Handler
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Set_Default_Handler BusFault_Handler
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Set_Default_Handler UsageFault_Handler
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Set_Default_Handler SVC_Handler
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Set_Default_Handler DebugMon_Handler
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Set_Default_Handler PendSV_Handler
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Set_Default_Handler SysTick_Handler
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Set_Default_Handler WWDG1_IRQHandler ; Window WatchDog 1
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Set_Default_Handler PVD_AVD_IRQHandler ; PVD and AVD through EXTI Line detection
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Set_Default_Handler TAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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Set_Default_Handler RTC_WKUP_ALARM_IRQHandler ; RTC Wakeup and Alarm through the EXTI line
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Set_Default_Handler RESERVED4_IRQHandler ; Reserved
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Set_Default_Handler RCC_IRQHandler ; RCC
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Set_Default_Handler EXTI0_IRQHandler ; EXTI Line0
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Set_Default_Handler EXTI1_IRQHandler ; EXTI Line1
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Set_Default_Handler EXTI2_IRQHandler ; EXTI Line2
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Set_Default_Handler EXTI3_IRQHandler ; EXTI Line3
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Set_Default_Handler EXTI4_IRQHandler ; EXTI Line4
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Set_Default_Handler DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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Set_Default_Handler DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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Set_Default_Handler DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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Set_Default_Handler DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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Set_Default_Handler DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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Set_Default_Handler DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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Set_Default_Handler DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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Set_Default_Handler ADC1_IRQHandler ; ADC1
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Set_Default_Handler FDCAN1_IT0_IRQHandler ; FDCAN1 Interrupt line 0
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Set_Default_Handler FDCAN2_IT0_IRQHandler ; FDCAN2 Interrupt line 0
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Set_Default_Handler FDCAN1_IT1_IRQHandler ; FDCAN1 Interrupt line 1
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Set_Default_Handler FDCAN2_IT1_IRQHandler ; FDCAN2 Interrupt line 1
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Set_Default_Handler EXTI5_IRQHandler ; External Line5 interrupts through AIEC
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Set_Default_Handler TIM1_BRK_IRQHandler ; TIM1 Break interrupt
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Set_Default_Handler TIM1_UP_IRQHandler ; TIM1 Update Interrupt
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Set_Default_Handler TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
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Set_Default_Handler TIM1_CC_IRQHandler ; TIM1 Capture Compare
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Set_Default_Handler TIM2_IRQHandler ; TIM2
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Set_Default_Handler TIM3_IRQHandler ; TIM3
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Set_Default_Handler TIM4_IRQHandler ; TIM4
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Set_Default_Handler I2C1_EV_IRQHandler ; I2C1 Event
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Set_Default_Handler I2C1_ER_IRQHandler ; I2C1 Error
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Set_Default_Handler I2C2_EV_IRQHandler ; I2C2 Event
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Set_Default_Handler I2C2_ER_IRQHandler ; I2C2 Error
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Set_Default_Handler SPI1_IRQHandler ; SPI1
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Set_Default_Handler SPI2_IRQHandler ; SPI2
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Set_Default_Handler USART1_IRQHandler ; USART1
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Set_Default_Handler USART2_IRQHandler ; USART2
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Set_Default_Handler USART3_IRQHandler ; USART3
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Set_Default_Handler EXTI10_IRQHandler ; External Line10 interrupts through AIEC
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Set_Default_Handler RTC_TIMESTAMP_IRQHandler ; RTC TimeStamp through EXTI Line
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Set_Default_Handler EXTI11_IRQHandler ; External Line11 interrupts through AIEC
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Set_Default_Handler TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
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Set_Default_Handler TIM8_UP_IRQHandler ; TIM8 Update Interrupt
|
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Set_Default_Handler TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
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Set_Default_Handler TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
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Set_Default_Handler DMA1_Stream7_IRQHandler ; DMA1 Stream7
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Set_Default_Handler FMC_IRQHandler ; FMC
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Set_Default_Handler SDMMC1_IRQHandler ; SDMMC1
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||||
Set_Default_Handler TIM5_IRQHandler ; TIM5
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||||
Set_Default_Handler SPI3_IRQHandler ; SPI3
|
||||
Set_Default_Handler UART4_IRQHandler ; UART4
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||||
Set_Default_Handler UART5_IRQHandler ; UART5
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||||
Set_Default_Handler TIM6_IRQHandler ; TIM6
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||||
Set_Default_Handler TIM7_IRQHandler ; TIM7
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||||
Set_Default_Handler DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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||||
Set_Default_Handler DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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||||
Set_Default_Handler DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
Set_Default_Handler DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
Set_Default_Handler DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
Set_Default_Handler ETH1_IRQHandler ; Ethernet
|
||||
Set_Default_Handler ETH1_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
Set_Default_Handler FDCAN_CAL_IRQHandler ; FDCAN Calibration
|
||||
Set_Default_Handler EXTI6_IRQHandler ; EXTI Line6 interrupts through AIEC
|
||||
Set_Default_Handler EXTI7_IRQHandler ; EXTI Line7 interrupts through AIEC
|
||||
Set_Default_Handler EXTI8_IRQHandler ; EXTI Line8 interrupts through AIEC
|
||||
Set_Default_Handler EXTI9_IRQHandler ; EXTI Line9 interrupts through AIEC
|
||||
Set_Default_Handler DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
Set_Default_Handler DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
Set_Default_Handler DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
Set_Default_Handler USART6_IRQHandler ; USART6
|
||||
Set_Default_Handler I2C3_EV_IRQHandler ; I2C3 event
|
||||
Set_Default_Handler I2C3_ER_IRQHandler ; I2C3 error
|
||||
Set_Default_Handler USBH_OHCI_IRQHandler ; USB Host OHCI
|
||||
Set_Default_Handler USBH_EHCI_IRQHandler ; USB Host EHCI
|
||||
Set_Default_Handler EXTI12_IRQHandler ; EXTI Line12 interrupts through AIEC
|
||||
Set_Default_Handler EXTI13_IRQHandler ; EXTI Line13 interrupts through AIEC
|
||||
Set_Default_Handler DCMI_IRQHandler ; DCMI
|
||||
Set_Default_Handler CRYP1_IRQHandler ; Crypto1 global interrupt
|
||||
Set_Default_Handler HASH1_IRQHandler ; Crypto Hash1 interrupt
|
||||
Set_Default_Handler FPU_IRQHandler ; FPU
|
||||
Set_Default_Handler UART7_IRQHandler ; UART7
|
||||
Set_Default_Handler UART8_IRQHandler ; UART8
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||||
Set_Default_Handler SPI4_IRQHandler ; SPI4
|
||||
Set_Default_Handler SPI5_IRQHandler ; SPI5
|
||||
Set_Default_Handler SPI6_IRQHandler ; SPI6
|
||||
Set_Default_Handler SAI1_IRQHandler ; SAI1
|
||||
Set_Default_Handler LTDC_IRQHandler ; LTDC
|
||||
Set_Default_Handler LTDC_ER_IRQHandler ; LTDC error
|
||||
Set_Default_Handler ADC2_IRQHandler ; ADC2
|
||||
Set_Default_Handler SAI2_IRQHandler ; SAI2
|
||||
Set_Default_Handler QUADSPI_IRQHandler ; QUADSPI
|
||||
Set_Default_Handler LPTIM1_IRQHandler ; LPTIM1 global interrupt
|
||||
Set_Default_Handler CEC_IRQHandler ; HDMI_CEC
|
||||
Set_Default_Handler I2C4_EV_IRQHandler ; I2C4 Event
|
||||
Set_Default_Handler I2C4_ER_IRQHandler ; I2C4 Error
|
||||
Set_Default_Handler SPDIF_RX_IRQHandler ; SPDIF_RX
|
||||
Set_Default_Handler OTG_IRQHandler ; USB On The Go HS global interrupt
|
||||
Set_Default_Handler RESERVED99_IRQHandler ; Reserved
|
||||
Set_Default_Handler IPCC_RX0_IRQHandler ; Mailbox RX0 Free interrupt
|
||||
Set_Default_Handler IPCC_TX0_IRQHandler ; Mailbox TX0 Free interrupt
|
||||
Set_Default_Handler DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
|
||||
Set_Default_Handler IPCC_RX1_IRQHandler ; Mailbox RX1 Free interrupt
|
||||
Set_Default_Handler IPCC_TX1_IRQHandler ; Mailbox TX1 Free interrupt
|
||||
Set_Default_Handler CRYP2_IRQHandler ; Crypto2 global interrupt
|
||||
Set_Default_Handler HASH2_IRQHandler ; Crypto Hash2 interrupt
|
||||
Set_Default_Handler I2C5_EV_IRQHandler ; I2C5 Event Interrupt
|
||||
Set_Default_Handler I2C5_ER_IRQHandler ; I2C5 Error Interrupt
|
||||
Set_Default_Handler GPU_IRQHandler ; GPU Global Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
|
||||
Set_Default_Handler SAI3_IRQHandler ; SAI3 global Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
|
||||
Set_Default_Handler TIM15_IRQHandler ; TIM15 global Interrupt
|
||||
Set_Default_Handler TIM16_IRQHandler ; TIM16 global Interrupt
|
||||
Set_Default_Handler TIM17_IRQHandler ; TIM17 global Interrupt
|
||||
Set_Default_Handler TIM12_IRQHandler ; TIM12 global Interrupt
|
||||
Set_Default_Handler MDIOS_IRQHandler ; MDIOS global Interrupt
|
||||
Set_Default_Handler EXTI14_IRQHandler ; EXTI Line14 interrupts through AIEC
|
||||
Set_Default_Handler MDMA_IRQHandler ; MDMA global Interrupt
|
||||
Set_Default_Handler DSI_IRQHandler ; DSI global Interrupt
|
||||
Set_Default_Handler SDMMC2_IRQHandler ; SDMMC2 global Interrupt
|
||||
Set_Default_Handler HSEM_IT2_IRQHandler ; HSEM global Interrupt
|
||||
Set_Default_Handler DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
|
||||
Set_Default_Handler EXTI15_IRQHandler ; EXTI Line15 interrupts through AIEC
|
||||
Set_Default_Handler nCTIIRQ1_IRQHandler ; Cortex-M4 CTI interrupt 1
|
||||
Set_Default_Handler nCTIIRQ2_IRQHandler ; Cortex-M4 CTI interrupt 2
|
||||
Set_Default_Handler TIM13_IRQHandler ; TIM13 global interrupt
|
||||
Set_Default_Handler TIM14_IRQHandler ; TIM14 global interrupt
|
||||
Set_Default_Handler DAC_IRQHandler ; DAC1 and DAC2 underrun error interrupts
|
||||
Set_Default_Handler RNG1_IRQHandler ; RNG1 interrupt
|
||||
Set_Default_Handler RNG2_IRQHandler ; RNG2 interrupt
|
||||
Set_Default_Handler I2C6_EV_IRQHandler ; I2C6 Event Interrupt
|
||||
Set_Default_Handler I2C6_ER_IRQHandler ; I2C6 Error Interrupt
|
||||
Set_Default_Handler SDMMC3_IRQHandler ; SDMMC3 global Interrupt
|
||||
Set_Default_Handler LPTIM2_IRQHandler ; LPTIM2 global interrupt
|
||||
Set_Default_Handler LPTIM3_IRQHandler ; LPTIM3 global interrupt
|
||||
Set_Default_Handler LPTIM4_IRQHandler ; LPTIM4 global interrupt
|
||||
Set_Default_Handler LPTIM5_IRQHandler ; LPTIM5 global interrupt
|
||||
Set_Default_Handler ETH1_LPI_IRQHandler ; Reserved
|
||||
Set_Default_Handler RESERVED143_IRQHandler ; Reserved
|
||||
Set_Default_Handler MPU_SEV_IRQHandler ; MPU Send Event through AIEC
|
||||
Set_Default_Handler RCC_WAKEUP_IRQHandler ; RCC Wake up interrupt
|
||||
Set_Default_Handler SAI4_IRQHandler ; SAI4 global interrupt
|
||||
Set_Default_Handler DTS_IRQHandler ; Temperature sensor interrupt
|
||||
Set_Default_Handler RESERVED148_IRQHandler ; Reserved
|
||||
Set_Default_Handler WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User setup Stack & Heap
|
||||
|
||||
EXPORT __stack_limit
|
||||
EXPORT __initial_sp
|
||||
IF Heap_Size != 0 ; Heap is provided
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Abstract : Linker script for STM32MP1 series
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed “as is,” without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the License; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x10040000; /* end of RAM */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000298
|
||||
m_text (RX) : ORIGIN = 0x10000000, LENGTH = 0x00020000
|
||||
m_data (RW) : ORIGIN = 0x10020000, LENGTH = 0x00020000
|
||||
m_ipc_shm (RW) : ORIGIN = 0x10040000, LENGTH = 0x00008000
|
||||
}
|
||||
|
||||
/* Symbols needed for OpenAMP to enable rpmsg */
|
||||
__OPENAMP_region_start__ = ORIGIN(m_ipc_shm);
|
||||
__OPENAMP_region_end__ = ORIGIN(m_ipc_shm)+LENGTH(m_ipc_shm);
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into ROM memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
|
||||
/* The program code and other data into ROM memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} > m_text
|
||||
|
||||
/* Constant data into ROM memory*/
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
__DATA_ROM = .;
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections */
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (_edata - _sdata);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
.resource_table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP (*(.resource_table*))
|
||||
. = ALIGN(4);
|
||||
} > m_data
|
||||
|
||||
|
||||
/* Uninitialized data section into RAM memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} > m_data
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} > m_data
|
||||
|
||||
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
}
|
||||
@@ -0,0 +1,792 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32mp15xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32MP15xx Devices vector table for GCC based toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .startup_copro_fw.Reset_Handler,"ax"
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* _sidata: End of code section, i.e., begin of data sections to copy from.
|
||||
* _sdata/_edata: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
|
||||
bl SystemInit
|
||||
// ldr r0, =SystemInit
|
||||
// blx r0
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
// ldr r0, =__libc_init_array
|
||||
// blx r0
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
//ldr r0, =main
|
||||
//blx r0
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack // Top of Stack
|
||||
.word Reset_Handler // Reset Handler
|
||||
.word NMI_Handler // NMI Handler
|
||||
.word HardFault_Handler // Hard Fault Handler
|
||||
.word MemManage_Handler // MPU Fault Handler
|
||||
.word BusFault_Handler // Bus Fault Handler
|
||||
.word UsageFault_Handler // Usage Fault Handler
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word 0 // Reserved
|
||||
.word SVC_Handler // SVCall Handler
|
||||
.word DebugMon_Handler // Debug Monitor Handler
|
||||
.word 0 // Reserved
|
||||
.word PendSV_Handler // PendSV Handler
|
||||
.word SysTick_Handler // SysTick Handler
|
||||
|
||||
// External Interrupts
|
||||
.word WWDG1_IRQHandler // Window WatchDog 1
|
||||
.word PVD_AVD_IRQHandler // PVD and AVD through EXTI Line detection
|
||||
.word TAMP_IRQHandler // Tamper and TimeStamps through the EXTI line
|
||||
.word RTC_WKUP_ALARM_IRQHandler // RTC Wakeup and Alarm through the EXTI line
|
||||
.word RESERVED4_IRQHandler // Reserved
|
||||
.word RCC_IRQHandler // RCC
|
||||
.word EXTI0_IRQHandler // EXTI Line0
|
||||
.word EXTI1_IRQHandler // EXTI Line1
|
||||
.word EXTI2_IRQHandler // EXTI Line2
|
||||
.word EXTI3_IRQHandler // EXTI Line3
|
||||
.word EXTI4_IRQHandler // EXTI Line4
|
||||
.word DMA1_Stream0_IRQHandler // DMA1 Stream 0
|
||||
.word DMA1_Stream1_IRQHandler // DMA1 Stream 1
|
||||
.word DMA1_Stream2_IRQHandler // DMA1 Stream 2
|
||||
.word DMA1_Stream3_IRQHandler // DMA1 Stream 3
|
||||
.word DMA1_Stream4_IRQHandler // DMA1 Stream 4
|
||||
.word DMA1_Stream5_IRQHandler // DMA1 Stream 5
|
||||
.word DMA1_Stream6_IRQHandler // DMA1 Stream 6
|
||||
.word ADC1_IRQHandler // ADC1
|
||||
.word FDCAN1_IT0_IRQHandler // FDCAN1 Interrupt line 0
|
||||
.word FDCAN2_IT0_IRQHandler // FDCAN2 Interrupt line 0
|
||||
.word FDCAN1_IT1_IRQHandler // FDCAN1 Interrupt line 1
|
||||
.word FDCAN2_IT1_IRQHandler // FDCAN2 Interrupt line 1
|
||||
.word EXTI5_IRQHandler // External Line5 interrupts through AIEC
|
||||
.word TIM1_BRK_IRQHandler // TIM1 Break interrupt
|
||||
.word TIM1_UP_IRQHandler // TIM1 Update Interrupt
|
||||
.word TIM1_TRG_COM_IRQHandler // TIM1 Trigger and Commutation Interrupt
|
||||
.word TIM1_CC_IRQHandler // TIM1 Capture Compare
|
||||
.word TIM2_IRQHandler // TIM2
|
||||
.word TIM3_IRQHandler // TIM3
|
||||
.word TIM4_IRQHandler // TIM4
|
||||
.word I2C1_EV_IRQHandler // I2C1 Event
|
||||
.word I2C1_ER_IRQHandler // I2C1 Error
|
||||
.word I2C2_EV_IRQHandler // I2C2 Event
|
||||
.word I2C2_ER_IRQHandler // I2C2 Error
|
||||
.word SPI1_IRQHandler // SPI1
|
||||
.word SPI2_IRQHandler // SPI2
|
||||
.word USART1_IRQHandler // USART1
|
||||
.word USART2_IRQHandler // USART2
|
||||
.word USART3_IRQHandler // USART3
|
||||
.word EXTI10_IRQHandler // External Line10 interrupts through AIEC
|
||||
.word RTC_TIMESTAMP_IRQHandler // RTC TimeStamp through EXTI Line
|
||||
.word EXTI11_IRQHandler // External Line11 interrupts through AIEC
|
||||
.word TIM8_BRK_IRQHandler // TIM8 Break Interrupt
|
||||
.word TIM8_UP_IRQHandler // TIM8 Update Interrupt
|
||||
.word TIM8_TRG_COM_IRQHandler // TIM8 Trigger and Commutation Interrupt
|
||||
.word TIM8_CC_IRQHandler // TIM8 Capture Compare Interrupt
|
||||
.word DMA1_Stream7_IRQHandler // DMA1 Stream7
|
||||
.word FMC_IRQHandler // FMC
|
||||
.word SDMMC1_IRQHandler // SDMMC1
|
||||
.word TIM5_IRQHandler // TIM5
|
||||
.word SPI3_IRQHandler // SPI3
|
||||
.word UART4_IRQHandler // UART4
|
||||
.word UART5_IRQHandler // UART5
|
||||
.word TIM6_IRQHandler // TIM6
|
||||
.word TIM7_IRQHandler // TIM7
|
||||
.word DMA2_Stream0_IRQHandler // DMA2 Stream 0
|
||||
.word DMA2_Stream1_IRQHandler // DMA2 Stream 1
|
||||
.word DMA2_Stream2_IRQHandler // DMA2 Stream 2
|
||||
.word DMA2_Stream3_IRQHandler // DMA2 Stream 3
|
||||
.word DMA2_Stream4_IRQHandler // DMA2 Stream 4
|
||||
.word ETH1_IRQHandler // Ethernet
|
||||
.word ETH1_WKUP_IRQHandler // Ethernet Wakeup through EXTI line
|
||||
.word FDCAN_CAL_IRQHandler // FDCAN Calibration
|
||||
.word EXTI6_IRQHandler // EXTI Line6 interrupts through AIEC
|
||||
.word EXTI7_IRQHandler // EXTI Line7 interrupts through AIEC
|
||||
.word EXTI8_IRQHandler // EXTI Line8 interrupts through AIEC
|
||||
.word EXTI9_IRQHandler // EXTI Line9 interrupts through AIEC
|
||||
.word DMA2_Stream5_IRQHandler // DMA2 Stream 5
|
||||
.word DMA2_Stream6_IRQHandler // DMA2 Stream 6
|
||||
.word DMA2_Stream7_IRQHandler // DMA2 Stream 7
|
||||
.word USART6_IRQHandler // USART6
|
||||
.word I2C3_EV_IRQHandler // I2C3 event
|
||||
.word I2C3_ER_IRQHandler // I2C3 error
|
||||
.word USBH_OHCI_IRQHandler // USB Host OHCI
|
||||
.word USBH_EHCI_IRQHandler // USB Host EHCI
|
||||
.word EXTI12_IRQHandler // EXTI Line12 interrupts through AIEC
|
||||
.word EXTI13_IRQHandler // EXTI Line13 interrupts through AIEC
|
||||
.word DCMI_IRQHandler // DCMI
|
||||
.word CRYP1_IRQHandler // Crypto1 global interrupt
|
||||
.word HASH1_IRQHandler // Crypto Hash1 interrupt
|
||||
.word FPU_IRQHandler // FPU
|
||||
.word UART7_IRQHandler // UART7
|
||||
.word UART8_IRQHandler // UART8
|
||||
.word SPI4_IRQHandler // SPI4
|
||||
.word SPI5_IRQHandler // SPI5
|
||||
.word SPI6_IRQHandler // SPI6
|
||||
.word SAI1_IRQHandler // SAI1
|
||||
.word LTDC_IRQHandler // LTDC
|
||||
.word LTDC_ER_IRQHandler // LTDC error
|
||||
.word ADC2_IRQHandler // ADC2
|
||||
.word SAI2_IRQHandler // SAI2
|
||||
.word QUADSPI_IRQHandler // QUADSPI
|
||||
.word LPTIM1_IRQHandler // LPTIM1 global interrupt
|
||||
.word CEC_IRQHandler // HDMI_CEC
|
||||
.word I2C4_EV_IRQHandler // I2C4 Event
|
||||
.word I2C4_ER_IRQHandler // I2C4 Error
|
||||
.word SPDIF_RX_IRQHandler // SPDIF_RX
|
||||
.word OTG_IRQHandler // USB On The Go HS global interrupt
|
||||
.word RESERVED99_IRQHandler // Reserved
|
||||
.word IPCC_RX0_IRQHandler // Mailbox RX0 Free interrupt
|
||||
.word IPCC_TX0_IRQHandler // Mailbox TX0 Free interrupt
|
||||
.word DMAMUX1_OVR_IRQHandler // DMAMUX1 Overrun interrupt
|
||||
.word IPCC_RX1_IRQHandler // Mailbox RX1 Free interrupt
|
||||
.word IPCC_TX1_IRQHandler // Mailbox TX1 Free interrupt
|
||||
.word CRYP2_IRQHandler // Crypto2 global interrupt
|
||||
.word HASH2_IRQHandler // Crypto Hash2 interrupt
|
||||
.word I2C5_EV_IRQHandler // I2C5 Event Interrupt
|
||||
.word I2C5_ER_IRQHandler // I2C5 Error Interrupt
|
||||
.word GPU_IRQHandler // GPU Global Interrupt
|
||||
.word DFSDM1_FLT0_IRQHandler // DFSDM Filter0 Interrupt
|
||||
.word DFSDM1_FLT1_IRQHandler // DFSDM Filter1 Interrupt
|
||||
.word DFSDM1_FLT2_IRQHandler // DFSDM Filter2 Interrupt
|
||||
.word DFSDM1_FLT3_IRQHandler // DFSDM Filter3 Interrupt
|
||||
.word SAI3_IRQHandler // SAI3 global Interrupt
|
||||
.word DFSDM1_FLT4_IRQHandler // DFSDM Filter4 Interrupt
|
||||
.word TIM15_IRQHandler // TIM15 global Interrupt
|
||||
.word TIM16_IRQHandler // TIM16 global Interrupt
|
||||
.word TIM17_IRQHandler // TIM17 global Interrupt
|
||||
.word TIM12_IRQHandler // TIM12 global Interrupt
|
||||
.word MDIOS_IRQHandler // MDIOS global Interrupt
|
||||
.word EXTI14_IRQHandler // EXTI Line14 interrupts through AIEC
|
||||
.word MDMA_IRQHandler // MDMA global Interrupt
|
||||
.word DSI_IRQHandler // DSI global Interrupt
|
||||
.word SDMMC2_IRQHandler // SDMMC2 global Interrupt
|
||||
.word HSEM_IT2_IRQHandler // HSEM global Interrupt
|
||||
.word DFSDM1_FLT5_IRQHandler // DFSDM Filter5 Interrupt
|
||||
.word EXTI15_IRQHandler // EXTI Line15 interrupts through AIEC
|
||||
.word nCTIIRQ1_IRQHandler // Cortex-M4 CTI interrupt 1
|
||||
.word nCTIIRQ2_IRQHandler // Cortex-M4 CTI interrupt 2
|
||||
.word TIM13_IRQHandler // TIM13 global interrupt
|
||||
.word TIM14_IRQHandler // TIM14 global interrupt
|
||||
.word DAC_IRQHandler // DAC1 and DAC2 underrun error interrupts
|
||||
.word RNG1_IRQHandler // RNG1 interrupt
|
||||
.word RNG2_IRQHandler // RNG2 interrupt
|
||||
.word I2C6_EV_IRQHandler // I2C6 Event Interrupt
|
||||
.word I2C6_ER_IRQHandler // I2C6 Error Interrupt
|
||||
.word SDMMC3_IRQHandler // SDMMC3 global Interrupt
|
||||
.word LPTIM2_IRQHandler // LPTIM2 global interrupt
|
||||
.word LPTIM3_IRQHandler // LPTIM3 global interrupt
|
||||
.word LPTIM4_IRQHandler // LPTIM4 global interrupt
|
||||
.word LPTIM5_IRQHandler // LPTIM5 global interrupt
|
||||
.word ETH1_LPI_IRQHandler // ETH1_LPI interrupt
|
||||
.word RESERVED143_IRQHandler // Reserved
|
||||
.word MPU_SEV_IRQHandler // MPU Send Event through AIEC
|
||||
.word RCC_WAKEUP_IRQHandler // RCC Wake up interrupt
|
||||
.word SAI4_IRQHandler // SAI4 global interrupt
|
||||
.word DTS_IRQHandler // Temperature sensor interrupt
|
||||
.word RESERVED148_IRQHandler // Reserved
|
||||
.word WAKEUP_PIN_IRQHandler // Interrupt for all 6 wake-up pins
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak RESERVED4_IRQHandler
|
||||
.thumb_set RESERVED4_IRQHandler,Default_Handler
|
||||
|
||||
.weak RESERVED99_IRQHandler
|
||||
.thumb_set RESERVED99_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH1_LPI_IRQHandler
|
||||
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak RESERVED143_IRQHandler
|
||||
.thumb_set RESERVED143_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG1_IRQHandler
|
||||
.thumb_set WWDG1_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_IRQHandler
|
||||
.thumb_set TAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_ALARM_IRQHandler
|
||||
.thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC2_IRQHandler
|
||||
.thumb_set ADC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_IRQHandler
|
||||
.thumb_set EXTI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_IRQHandler
|
||||
.thumb_set EXTI10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_TIMESTAMP_IRQHandler
|
||||
.thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI11_IRQHandler
|
||||
.thumb_set EXTI11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH1_IRQHandler
|
||||
.thumb_set ETH1_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH1_WKUP_IRQHandler
|
||||
.thumb_set ETH1_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH1_LPI_IRQHandler
|
||||
.thumb_set ETH1_LPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI6_IRQHandler
|
||||
.thumb_set EXTI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI7_IRQHandler
|
||||
.thumb_set EXTI7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI8_IRQHandler
|
||||
.thumb_set EXTI8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_IRQHandler
|
||||
.thumb_set EXTI9_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBH_OHCI_IRQHandler
|
||||
.thumb_set USBH_OHCI_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBH_EHCI_IRQHandler
|
||||
.thumb_set USBH_EHCI_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI12_IRQHandler
|
||||
.thumb_set EXTI12_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI13_IRQHandler
|
||||
.thumb_set EXTI13_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP1_IRQHandler
|
||||
.thumb_set CRYP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH1_IRQHandler
|
||||
.thumb_set HASH1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_IRQHandler
|
||||
.thumb_set OTG_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_RX0_IRQHandler
|
||||
.thumb_set IPCC_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_TX0_IRQHandler
|
||||
.thumb_set IPCC_TX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_RX1_IRQHandler
|
||||
.thumb_set IPCC_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_TX1_IRQHandler
|
||||
.thumb_set IPCC_TX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP2_IRQHandler
|
||||
.thumb_set CRYP2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH2_IRQHandler
|
||||
.thumb_set HASH2_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C5_EV_IRQHandler
|
||||
.thumb_set I2C5_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C5_ER_IRQHandler
|
||||
.thumb_set I2C5_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak GPU_IRQHandler
|
||||
.thumb_set GPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI3_IRQHandler
|
||||
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT4_IRQHandler
|
||||
.thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM12_IRQHandler
|
||||
.thumb_set TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI14_IRQHandler
|
||||
.thumb_set EXTI14_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DSI_IRQHandler
|
||||
.thumb_set DSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IT2_IRQHandler
|
||||
.thumb_set HSEM_IT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT5_IRQHandler
|
||||
.thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_IRQHandler
|
||||
.thumb_set EXTI15_IRQHandler,Default_Handler
|
||||
|
||||
.weak nCTIIRQ1_IRQHandler
|
||||
.thumb_set nCTIIRQ1_IRQHandler,Default_Handler
|
||||
|
||||
.weak nCTIIRQ2_IRQHandler
|
||||
.thumb_set nCTIIRQ2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM13_IRQHandler
|
||||
.thumb_set TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak DAC_IRQHandler
|
||||
.thumb_set DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG1_IRQHandler
|
||||
.thumb_set RNG1_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG2_IRQHandler
|
||||
.thumb_set RNG2_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C6_EV_IRQHandler
|
||||
.thumb_set I2C6_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C6_ER_IRQHandler
|
||||
.thumb_set I2C6_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC3_IRQHandler
|
||||
.thumb_set SDMMC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak MPU_SEV_IRQHandler
|
||||
.thumb_set MPU_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_WAKEUP_IRQHandler
|
||||
.thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DTS_IRQHandler
|
||||
.thumb_set DTS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RESERVED148_IRQHandler
|
||||
.thumb_set RESERVED148_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_text_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_text_end__ = 0x00008000;
|
||||
define symbol __ICFEDIT_region_data_start__ = 0x00008000;
|
||||
define symbol __ICFEDIT_region_data_end__ = 0x00010000;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region text_region = mem:[from __ICFEDIT_region_text_start__ to __ICFEDIT_region_text_end__];
|
||||
define region data_region = mem:[from __ICFEDIT_region_data_start__ to __ICFEDIT_region_data_end__];
|
||||
|
||||
keep { section .resource_table };
|
||||
".resource_table" : place in data_region {section .resource_table};
|
||||
|
||||
/* Create region for OPENAMP */
|
||||
/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
|
||||
define symbol __OPENAMP_region_start__ = 0x10040000;
|
||||
define symbol __OPENAMP_region_size__ = 0x8000;
|
||||
export symbol __OPENAMP_region_start__;
|
||||
export symbol __OPENAMP_region_size__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in text_region { readonly };
|
||||
place in data_region { readwrite,
|
||||
block CSTACK, block HEAP};
|
||||
@@ -0,0 +1,40 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_text_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_text_end__ = 0x1001FFFF;
|
||||
define symbol __ICFEDIT_region_data_start__ = 0x10020000;
|
||||
define symbol __ICFEDIT_region_data_end__ = 0x1003FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region text_region = mem:[from __ICFEDIT_region_text_start__ to __ICFEDIT_region_text_end__];
|
||||
define region data_region = mem:[from __ICFEDIT_region_data_start__ to __ICFEDIT_region_data_end__];
|
||||
|
||||
keep { section .resource_table };
|
||||
".resource_table" : place in data_region {section .resource_table};
|
||||
|
||||
/* Create region for OPENAMP */
|
||||
/* !!! These 4 lines can be commented if OPENAMP is not used !!!*/
|
||||
define symbol __OPENAMP_region_start__ = 0x10040000;
|
||||
define symbol __OPENAMP_region_size__ = 0x8000;
|
||||
export symbol __OPENAMP_region_start__;
|
||||
export symbol __OPENAMP_region_size__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in text_region { readonly };
|
||||
place in data_region { readwrite,
|
||||
block CSTACK, block HEAP};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,290 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32mp1xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32mp1xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock frequency, it can
|
||||
* be used by the user application to setup
|
||||
* the SysTick timer or configure other
|
||||
* parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32mp1xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32mp1xx_hal.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on EVAL board as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x400. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) each time HAL_RCC_ClockConfig() is called to configure the system clock
|
||||
frequency
|
||||
Note: If you use this function to configure the system clock;
|
||||
then there is no need to call the first functions listed above,
|
||||
since SystemCoreClock variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = HSI_VALUE;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DATA_IN_ExtSRAM)
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32MP1xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the FPU setting, vector table location and External memory
|
||||
* configuration.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if defined (CORE_CM4)
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#if defined (VECT_TAB_SRAM)
|
||||
SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#endif
|
||||
/* Disable all interrupts and events */
|
||||
CLEAR_REG(EXTI_C2->IMR1);
|
||||
CLEAR_REG(EXTI_C2->IMR2);
|
||||
CLEAR_REG(EXTI_C2->IMR3);
|
||||
CLEAR_REG(EXTI_C2->EMR1);
|
||||
CLEAR_REG(EXTI_C2->EMR2);
|
||||
CLEAR_REG(EXTI_C2->EMR3);
|
||||
#else
|
||||
#error Please #define CORE_CM4
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock frequency (Hz),
|
||||
* it can be used by the user application to setup the SysTick timer or
|
||||
* configure other parameters.
|
||||
*
|
||||
* @note Each time the core clock changes, this function must be called to
|
||||
* update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the
|
||||
* HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the
|
||||
* HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is CSI, SystemCoreClock will contain the
|
||||
* CSI_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
|
||||
* HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
|
||||
* multiplied/divided by the PLL3 factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
|
||||
* (default value 64 MHz) but the real value may vary depending
|
||||
* on the variations in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
|
||||
* (default value 24 MHz), user has to ensure that HSE_VALUE is
|
||||
* same as the real frequency of the crystal used. Otherwise, this
|
||||
* function may have wrong result.
|
||||
*
|
||||
* (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
|
||||
* (default value 4 MHz)but the real value may vary depending
|
||||
* on the variations in voltage and temperature.
|
||||
*
|
||||
* - The result of this function could be not correct when using
|
||||
* fractional value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t pllsource, pll3m, pll3fracen;
|
||||
float fracn1, pll3vco;
|
||||
|
||||
switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
|
||||
break;
|
||||
|
||||
case 0x01: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x02: /* CSI used as system clock source */
|
||||
SystemCoreClock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x03: /* PLL3_P used as system clock source */
|
||||
pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
|
||||
pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
|
||||
pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
|
||||
fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
|
||||
pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x1FFF));
|
||||
|
||||
if (pll3m != 0U)
|
||||
{
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x00: /* HSI used as PLL clock source */
|
||||
pll3vco *= (float)((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
|
||||
break;
|
||||
|
||||
case 0x01: /* HSE used as PLL clock source */
|
||||
pll3vco *= (float)(HSE_VALUE / pll3m);
|
||||
break;
|
||||
|
||||
case 0x02: /* CSI used as PLL clock source */
|
||||
pll3vco *= (float)(CSI_VALUE / pll3m);
|
||||
break;
|
||||
|
||||
case 0x03: /* No clock source for PLL */
|
||||
pll3vco = 0;
|
||||
break;
|
||||
}
|
||||
SystemCoreClock = (uint32_t)(pll3vco/ ((float)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = 0U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute mcu_ck */
|
||||
SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
|
||||
}
|
||||
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32mp15xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on Eval boards
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user