2023-06-10 11:52:00 +08:00
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/**
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******************************************************************************
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2023-09-09 17:27:06 +08:00
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* @file stm32f10x_i2c.h
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2023-06-10 11:52:00 +08:00
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* @author MCD Application Team
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2023-09-09 17:27:06 +08:00
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* @version V3.5.0
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* @date 11-March-2011
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2023-06-10 11:52:00 +08:00
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* @brief This file contains all the functions prototypes for the I2C firmware
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* library.
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******************************************************************************
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* @attention
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*
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2023-09-09 17:27:06 +08:00
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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2023-06-10 11:52:00 +08:00
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*
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2023-09-09 17:27:06 +08:00
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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2023-06-10 11:52:00 +08:00
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/* Define to prevent recursive inclusion -------------------------------------*/
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2023-09-09 17:27:06 +08:00
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#ifndef __STM32F10x_I2C_H
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#define __STM32F10x_I2C_H
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2023-06-10 11:52:00 +08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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2023-09-09 17:27:06 +08:00
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#include "stm32f10x.h"
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2023-06-10 11:52:00 +08:00
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2023-09-09 17:27:06 +08:00
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/** @addtogroup STM32F10x_StdPeriph_Driver
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2023-06-10 11:52:00 +08:00
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* @{
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*/
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/** @addtogroup I2C
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* @{
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*/
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2023-09-09 17:27:06 +08:00
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/** @defgroup I2C_Exported_Types
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* @{
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*/
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2023-06-10 11:52:00 +08:00
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/**
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* @brief I2C Init structure definition
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*/
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typedef struct
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{
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uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
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This parameter must be set to a value lower than 400kHz */
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uint16_t I2C_Mode; /*!< Specifies the I2C mode.
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This parameter can be a value of @ref I2C_mode */
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uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
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This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
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uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
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This parameter can be a 7-bit or 10-bit address. */
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uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
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This parameter can be a value of @ref I2C_acknowledgement */
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uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
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This parameter can be a value of @ref I2C_acknowledged_address */
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}I2C_InitTypeDef;
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2023-09-09 17:27:06 +08:00
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/**
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* @}
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*/
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2023-06-10 11:52:00 +08:00
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/** @defgroup I2C_Exported_Constants
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* @{
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*/
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#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
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((PERIPH) == I2C2))
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/** @defgroup I2C_mode
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* @{
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*/
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#define I2C_Mode_I2C ((uint16_t)0x0000)
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#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
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#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
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#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
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((MODE) == I2C_Mode_SMBusDevice) || \
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((MODE) == I2C_Mode_SMBusHost))
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/**
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* @}
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*/
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/** @defgroup I2C_duty_cycle_in_fast_mode
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* @{
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*/
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#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
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#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
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#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
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((CYCLE) == I2C_DutyCycle_2))
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/**
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* @}
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*/
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/** @defgroup I2C_acknowledgement
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* @{
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*/
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#define I2C_Ack_Enable ((uint16_t)0x0400)
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#define I2C_Ack_Disable ((uint16_t)0x0000)
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#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
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((STATE) == I2C_Ack_Disable))
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/**
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* @}
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*/
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/** @defgroup I2C_transfer_direction
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* @{
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*/
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#define I2C_Direction_Transmitter ((uint8_t)0x00)
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#define I2C_Direction_Receiver ((uint8_t)0x01)
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#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
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((DIRECTION) == I2C_Direction_Receiver))
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/**
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* @}
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*/
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/** @defgroup I2C_acknowledged_address
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* @{
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*/
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#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
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#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
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#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
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((ADDRESS) == I2C_AcknowledgedAddress_10bit))
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/**
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* @}
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*/
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/** @defgroup I2C_registers
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* @{
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*/
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#define I2C_Register_CR1 ((uint8_t)0x00)
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#define I2C_Register_CR2 ((uint8_t)0x04)
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#define I2C_Register_OAR1 ((uint8_t)0x08)
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#define I2C_Register_OAR2 ((uint8_t)0x0C)
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#define I2C_Register_DR ((uint8_t)0x10)
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#define I2C_Register_SR1 ((uint8_t)0x14)
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#define I2C_Register_SR2 ((uint8_t)0x18)
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#define I2C_Register_CCR ((uint8_t)0x1C)
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#define I2C_Register_TRISE ((uint8_t)0x20)
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#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
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((REGISTER) == I2C_Register_CR2) || \
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((REGISTER) == I2C_Register_OAR1) || \
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((REGISTER) == I2C_Register_OAR2) || \
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((REGISTER) == I2C_Register_DR) || \
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((REGISTER) == I2C_Register_SR1) || \
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((REGISTER) == I2C_Register_SR2) || \
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((REGISTER) == I2C_Register_CCR) || \
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((REGISTER) == I2C_Register_TRISE))
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/**
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* @}
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*/
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/** @defgroup I2C_SMBus_alert_pin_level
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* @{
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*/
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#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
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#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
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#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
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((ALERT) == I2C_SMBusAlert_High))
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/**
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* @}
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*/
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/** @defgroup I2C_PEC_position
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* @{
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*/
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#define I2C_PECPosition_Next ((uint16_t)0x0800)
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#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
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#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
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((POSITION) == I2C_PECPosition_Current))
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/**
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* @}
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*/
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2023-09-09 17:27:06 +08:00
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/** @defgroup I2C_NCAK_position
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* @{
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*/
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#define I2C_NACKPosition_Next ((uint16_t)0x0800)
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#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
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#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
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((POSITION) == I2C_NACKPosition_Current))
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/**
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* @}
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*/
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2023-06-10 11:52:00 +08:00
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/** @defgroup I2C_interrupts_definition
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* @{
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*/
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#define I2C_IT_BUF ((uint16_t)0x0400)
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#define I2C_IT_EVT ((uint16_t)0x0200)
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#define I2C_IT_ERR ((uint16_t)0x0100)
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#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
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/**
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* @}
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*/
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/** @defgroup I2C_interrupts_definition
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* @{
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*/
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#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
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#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
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#define I2C_IT_PECERR ((uint32_t)0x01001000)
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#define I2C_IT_OVR ((uint32_t)0x01000800)
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#define I2C_IT_AF ((uint32_t)0x01000400)
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#define I2C_IT_ARLO ((uint32_t)0x01000200)
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#define I2C_IT_BERR ((uint32_t)0x01000100)
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#define I2C_IT_TXE ((uint32_t)0x06000080)
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#define I2C_IT_RXNE ((uint32_t)0x06000040)
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#define I2C_IT_STOPF ((uint32_t)0x02000010)
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#define I2C_IT_ADD10 ((uint32_t)0x02000008)
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#define I2C_IT_BTF ((uint32_t)0x02000004)
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#define I2C_IT_ADDR ((uint32_t)0x02000002)
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#define I2C_IT_SB ((uint32_t)0x02000001)
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#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
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#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
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((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
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((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
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((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
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((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
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((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
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((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
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/**
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* @}
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*/
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/** @defgroup I2C_flags_definition
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* @{
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*/
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/**
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* @brief SR2 register flags
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*/
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#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
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#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
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#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
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#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
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#define I2C_FLAG_TRA ((uint32_t)0x00040000)
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#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
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#define I2C_FLAG_MSL ((uint32_t)0x00010000)
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/**
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* @brief SR1 register flags
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*/
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#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
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#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
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#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
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#define I2C_FLAG_OVR ((uint32_t)0x10000800)
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#define I2C_FLAG_AF ((uint32_t)0x10000400)
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#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
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#define I2C_FLAG_BERR ((uint32_t)0x10000100)
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#define I2C_FLAG_TXE ((uint32_t)0x10000080)
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#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
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#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
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#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
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#define I2C_FLAG_BTF ((uint32_t)0x10000004)
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#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
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#define I2C_FLAG_SB ((uint32_t)0x10000001)
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#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
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#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
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((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
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((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
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((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
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((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
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((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
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((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
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((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
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((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
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((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
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((FLAG) == I2C_FLAG_SB))
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|
/**
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* @}
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*/
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/** @defgroup I2C_Events
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* @{
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*/
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2023-09-09 17:27:06 +08:00
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/*========================================
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I2C Master Events (Events grouped in order of communication)
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==========================================*/
|
2023-06-10 11:52:00 +08:00
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/**
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* @brief Communication start
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*
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* After sending the START condition (I2C_GenerateSTART() function) the master
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* has to wait for this event. It means that the Start condition has been correctly
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* released on the I2C bus (the bus is free, no other devices is communicating).
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*
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*/
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/* --EV5 */
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#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
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/**
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* @brief Address Acknowledge
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*
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* After checking on EV5 (start condition correctly released on the bus), the
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* master sends the address of the slave(s) with which it will communicate
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* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
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* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
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* his address. If an acknowledge is sent on the bus, one of the following events will
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* be set:
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*
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* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
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* event is set.
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*
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* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
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* is set
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*
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* 3) In case of 10-Bit addressing mode, the master (just after generating the START
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* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
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|
|
* function). Then master should wait on EV9. It means that the 10-bit addressing
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|
|
* header has been correctly sent on the bus. Then master should send the second part of
|
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|
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
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|
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* should wait for event EV6.
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*
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|
|
|
*/
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|
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/* --EV6 */
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#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
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|
|
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
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|
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/* --EV9 */
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#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
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|
|
/**
|
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|
|
* @brief Communication events
|
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|
|
*
|
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|
|
* If a communication is established (START condition generated and slave address
|
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|
|
|
* acknowledged) then the master has to check on one of the following events for
|
|
|
|
|
* communication procedures:
|
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|
|
*
|
|
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|
|
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
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|
|
|
* the data received from the slave (I2C_ReceiveData() function).
|
|
|
|
|
*
|
|
|
|
|
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
|
|
|
|
* function) then to wait on event EV8 or EV8_2.
|
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|
|
|
* These two events are similar:
|
|
|
|
|
* - EV8 means that the data has been written in the data register and is
|
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|
|
|
* being shifted out.
|
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|
|
* - EV8_2 means that the data has been physically shifted out and output
|
|
|
|
|
* on the bus.
|
|
|
|
|
* In most cases, using EV8 is sufficient for the application.
|
|
|
|
|
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
|
|
|
|
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
|
|
|
|
* (before Stop condition generation).
|
|
|
|
|
*
|
|
|
|
|
* @note In case the user software does not guarantee that this event EV7 is
|
2023-09-09 17:27:06 +08:00
|
|
|
* managed before the current byte end of transfer, then user may check on EV7
|
|
|
|
|
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
|
|
|
|
* In this case the communication may be slower.
|
2023-06-10 11:52:00 +08:00
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Master RECEIVER mode -----------------------------*/
|
|
|
|
|
/* --EV7 */
|
|
|
|
|
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
|
|
|
|
|
|
|
|
|
/* Master TRANSMITTER mode --------------------------*/
|
|
|
|
|
/* --EV8 */
|
|
|
|
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
|
|
|
|
/* --EV8_2 */
|
|
|
|
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
|
|
|
|
|
|
|
|
|
|
2023-09-09 17:27:06 +08:00
|
|
|
/*========================================
|
|
|
|
|
|
|
|
|
|
I2C Slave Events (Events grouped in order of communication)
|
|
|
|
|
==========================================*/
|
2023-06-10 11:52:00 +08:00
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Communication start events
|
|
|
|
|
*
|
|
|
|
|
* Wait on one of these events at the start of the communication. It means that
|
|
|
|
|
* the I2C peripheral detected a Start condition on the bus (generated by master
|
|
|
|
|
* device) followed by the peripheral address. The peripheral generates an ACK
|
|
|
|
|
* condition on the bus (if the acknowledge feature is enabled through function
|
|
|
|
|
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
|
|
|
|
*
|
|
|
|
|
* 1) In normal case (only one address managed by the slave), when the address
|
|
|
|
|
* sent by the master matches the own address of the peripheral (configured by
|
|
|
|
|
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
|
|
|
|
* (where XXX could be TRANSMITTER or RECEIVER).
|
|
|
|
|
*
|
|
|
|
|
* 2) In case the address sent by the master matches the second address of the
|
|
|
|
|
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
|
|
|
|
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
|
|
|
|
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
|
|
|
|
*
|
|
|
|
|
* 3) In case the address sent by the master is General Call (address 0x00) and
|
|
|
|
|
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
|
|
|
|
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* --EV1 (all the events below are variants of EV1) */
|
|
|
|
|
/* 1) Case of One Single Address managed by the slave */
|
|
|
|
|
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
|
|
|
|
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
|
|
|
|
|
|
|
|
|
/* 2) Case of Dual address managed by the slave */
|
|
|
|
|
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
|
|
|
|
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
|
|
|
|
|
|
|
|
|
/* 3) Case of General Call enabled for the slave */
|
|
|
|
|
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Communication events
|
|
|
|
|
*
|
|
|
|
|
* Wait on one of these events when EV1 has already been checked and:
|
|
|
|
|
*
|
|
|
|
|
* - Slave RECEIVER mode:
|
|
|
|
|
* - EV2: When the application is expecting a data byte to be received.
|
|
|
|
|
* - EV4: When the application is expecting the end of the communication: master
|
|
|
|
|
* sends a stop condition and data transmission is stopped.
|
|
|
|
|
*
|
|
|
|
|
* - Slave Transmitter mode:
|
|
|
|
|
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
|
|
|
|
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
|
|
|
|
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
|
|
|
|
* used when the user software doesn't guarantee the EV3 is managed before the
|
|
|
|
|
* current byte end of transfer.
|
|
|
|
|
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
|
|
|
|
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
|
|
|
|
* data bytes and expect a Stop condition on the bus.
|
|
|
|
|
*
|
|
|
|
|
* @note In case the user software does not guarantee that the event EV2 is
|
2023-09-09 17:27:06 +08:00
|
|
|
* managed before the current byte end of transfer, then user may check on EV2
|
|
|
|
|
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
|
|
|
|
* In this case the communication may be slower.
|
2023-06-10 11:52:00 +08:00
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Slave RECEIVER mode --------------------------*/
|
|
|
|
|
/* --EV2 */
|
|
|
|
|
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
|
|
|
|
/* --EV4 */
|
|
|
|
|
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
|
|
|
|
|
|
|
|
|
/* Slave TRANSMITTER mode -----------------------*/
|
|
|
|
|
/* --EV3 */
|
|
|
|
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
|
|
|
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
|
|
|
|
/* --EV3_2 */
|
|
|
|
|
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
|
|
|
|
|
2023-09-09 17:27:06 +08:00
|
|
|
/*=========================== End of Events Description ==========================================*/
|
2023-06-10 11:52:00 +08:00
|
|
|
|
|
|
|
|
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
|
|
|
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
|
|
|
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
|
|
|
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
|
|
|
|
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
|
|
|
|
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
|
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/** @defgroup I2C_own_address1
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
|
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/** @defgroup I2C_clock_speed
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
|
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
|
|
|
|
|
2023-09-09 17:27:06 +08:00
|
|
|
/** @defgroup I2C_Exported_Macros
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
2023-06-10 11:52:00 +08:00
|
|
|
|
2023-09-09 17:27:06 +08:00
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/** @defgroup I2C_Exported_Functions
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
2023-06-10 11:52:00 +08:00
|
|
|
|
2023-09-09 17:27:06 +08:00
|
|
|
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
2023-06-10 11:52:00 +08:00
|
|
|
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
|
|
|
|
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
|
|
|
|
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
2023-09-09 17:27:06 +08:00
|
|
|
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
|
|
|
|
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
2023-06-10 11:52:00 +08:00
|
|
|
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
|
|
|
|
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
|
|
|
|
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
|
|
|
|
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
|
|
|
|
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
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void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
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2023-09-09 17:27:06 +08:00
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void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
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void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
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uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
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void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
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uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
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2023-06-10 11:52:00 +08:00
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void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
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void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
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void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
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void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
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void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
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void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
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uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
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2023-09-09 17:27:06 +08:00
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void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
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void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
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void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
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2023-06-10 11:52:00 +08:00
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2023-09-09 17:27:06 +08:00
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/**
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* @brief
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****************************************************************************************
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*
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* I2C State Monitoring Functions
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*
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****************************************************************************************
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* This I2C driver provides three different ways for I2C state monitoring
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* depending on the application requirements and constraints:
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*
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*
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* 1) Basic state monitoring:
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* Using I2C_CheckEvent() function:
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* It compares the status registers (SR1 and SR2) content to a given event
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* (can be the combination of one or more flags).
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* It returns SUCCESS if the current status includes the given flags
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* and returns ERROR if one or more flags are missing in the current status.
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* - When to use:
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* - This function is suitable for most applications as well as for startup
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* activity since the events are fully described in the product reference manual
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* (RM0008).
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* - It is also suitable for users who need to define their own events.
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* - Limitations:
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* - If an error occurs (ie. error flags are set besides to the monitored flags),
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* the I2C_CheckEvent() function may return SUCCESS despite the communication
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* hold or corrupted real state.
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* In this case, it is advised to use error interrupts to monitor the error
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* events and handle them in the interrupt IRQ handler.
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*
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* @note
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* For error management, it is advised to use the following functions:
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* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
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* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
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* Where x is the peripheral instance (I2C1, I2C2 ...)
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* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
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* in order to determine which error occurred.
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* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
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* and/or I2C_GenerateStop() in order to clear the error flag and source,
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* and return to correct communication status.
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*
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*
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* 2) Advanced state monitoring:
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* Using the function I2C_GetLastEvent() which returns the image of both status
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* registers in a single word (uint32_t) (Status Register 2 value is shifted left
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* by 16 bits and concatenated to Status Register 1).
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* - When to use:
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* - This function is suitable for the same applications above but it allows to
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* overcome the limitations of I2C_GetFlagStatus() function (see below).
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* The returned value could be compared to events already defined in the
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* library (stm32f10x_i2c.h) or to custom values defined by user.
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* - This function is suitable when multiple flags are monitored at the same time.
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* - At the opposite of I2C_CheckEvent() function, this function allows user to
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* choose when an event is accepted (when all events flags are set and no
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* other flags are set or just when the needed flags are set like
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* I2C_CheckEvent() function).
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* - Limitations:
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* - User may need to define his own events.
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* - Same remark concerning the error management is applicable for this
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* function if user decides to check only regular communication flags (and
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* ignores error flags).
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*
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*
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* 3) Flag-based state monitoring:
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* Using the function I2C_GetFlagStatus() which simply returns the status of
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* one single flag (ie. I2C_FLAG_RXNE ...).
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* - When to use:
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* - This function could be used for specific applications or in debug phase.
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* - It is suitable when only one flag checking is needed (most I2C events
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* are monitored through multiple flags).
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* - Limitations:
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* - When calling this function, the Status register is accessed. Some flags are
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* cleared when the status register is accessed. So checking the status
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* of one Flag, may clear other ones.
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* - Function may need to be called twice or more in order to monitor one
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* single event.
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*
|
2023-06-10 11:52:00 +08:00
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*/
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2023-09-09 17:27:06 +08:00
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/**
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*
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* 1) Basic state monitoring
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*******************************************************************************
|
2023-06-10 11:52:00 +08:00
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*/
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ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
2023-09-09 17:27:06 +08:00
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/**
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*
|
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* 2) Advanced state monitoring
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*******************************************************************************
|
2023-06-10 11:52:00 +08:00
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*/
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uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
2023-09-09 17:27:06 +08:00
|
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/**
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*
|
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* 3) Flag-based state monitoring
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|
*******************************************************************************
|
2023-06-10 11:52:00 +08:00
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*/
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FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
2023-09-09 17:27:06 +08:00
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/**
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*
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|
*******************************************************************************
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*/
|
2023-06-10 11:52:00 +08:00
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void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
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ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
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void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
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|
#ifdef __cplusplus
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}
|
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#endif
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|
2023-09-09 17:27:06 +08:00
|
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#endif /*__STM32F10x_I2C_H */
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|
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/**
|
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|
|
* @}
|
|
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|
|
*/
|
2023-06-10 11:52:00 +08:00
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|
|
/**
|
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|
|
|
* @}
|
|
|
|
|
*/
|
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|
|
|
|
/**
|
|
|
|
|
* @}
|
|
|
|
|
*/
|
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|
2023-09-09 17:27:06 +08:00
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
