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andy
548
source/rt_thread/libcpu/arm/armv6/mmu.c
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548
source/rt_thread/libcpu/arm/armv6/mmu.c
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@@ -0,0 +1,548 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include "mmu.h"
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#ifdef __CC_ARM
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void mmu_setttbase(rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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value = 0x55555555;
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__asm volatile
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{
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mcr p15, 0, value, c3, c0, 0
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mcr p15, 0, i, c2, c0, 0
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}
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}
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void mmu_set_domain(rt_uint32_t i)
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{
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__asm volatile
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{
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mcr p15,0, i, c3, c0, 0
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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__asm volatile
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{
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mcr p15, 0, index, c7, c14, 2
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}
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while(ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c14, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c10, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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__asm volatile
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{
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MCR p15, 0, ptr, c7, c6, 1
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}
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_tlb()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c8, c7, 0
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}
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}
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void mmu_invalidate_icache()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c7, c5, 0
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}
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}
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void mmu_invalidate_dcache_all()
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{
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register rt_uint32_t value;
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value = 0;
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__asm volatile
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{
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mcr p15, 0, value, c7, c6, 0
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}
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}
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#elif defined(__GNUC__)
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void mmu_setttbase(register rt_uint32_t i)
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{
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register rt_uint32_t value;
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/* Invalidates all TLBs.Domain access is selected as
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* client by configuring domain access register,
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* in that case access controlled by permission value
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* set by page table entry
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*/
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value = 0;
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asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
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value = 0x55555555;
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asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
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asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* Enables the extended page tables to be configured for
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the hardware page translation mechanism, Subpage AP bits disabled */
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i |= (1 << 23); /* support for ARMv6 MMU features */
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i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while(ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
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{
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unsigned int ptr;
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ptr = buffer & ~(CACHE_LINE_SIZE - 1);
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while (ptr < buffer + size)
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
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ptr += CACHE_LINE_SIZE;
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}
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}
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void mmu_invalidate_tlb()
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{
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asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
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{
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asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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void mmu_invalidate_dcache_all()
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{
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asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
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}
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#endif
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/* level1 page table */
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static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024);
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/*
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* level2 page table
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* RT_MMU_PTE_SIZE must be 1024*n
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*/
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#define RT_MMU_PTE_SIZE 4096
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static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024);
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void mmu_create_pgd(struct mem_desc *mdesc)
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{
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volatile rt_uint32_t *pTT;
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volatile int i, nSec;
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pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
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nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
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for(i = 0; i <= nSec; i++)
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{
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*pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
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pTT++;
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}
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}
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void mmu_create_pte(struct mem_desc *mdesc)
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{
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volatile rt_uint32_t *pTT;
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volatile rt_uint32_t *p_pteentry;
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int i;
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rt_uint32_t vaddr;
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rt_uint32_t total_page = 0;
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rt_uint32_t pte_offset = 0;
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rt_uint32_t sect_attr = 0;
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total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
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pte_offset = mdesc->sect_attr & 0xfffffc00;
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sect_attr = mdesc->sect_attr & 0x3ff;
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vaddr = mdesc->vaddr_start;
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for(i = 0; i < total_page; i++)
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{
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pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
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if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
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{
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*pTT = pte_offset | sect_attr;
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p_pteentry = (rt_uint32_t *)pte_offset +
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((vaddr & 0x000ff000) >> 12);
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pte_offset += 1024;
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}
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else /* using old Level 1 page table item */
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{
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p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
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((vaddr & 0x000ff000) >> 12);
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}
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*p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
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vaddr += 0x1000;
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}
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}
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static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
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{
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rt_uint32_t pte_offset = 0;
|
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rt_uint32_t nsec = 0;
|
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/* set page table */
|
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for (; size > 0; size--)
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{
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if (mdesc->mapped_mode == PAGE_MAPPED)
|
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{
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nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
|
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mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
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pte_offset += nsec << 10;
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}
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if (pte_offset >= RT_MMU_PTE_SIZE)
|
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{
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rt_kprintf("PTE table size too little\n");
|
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RT_ASSERT(0);
|
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}
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mdesc++;
|
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}
|
||||
}
|
||||
|
||||
|
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
|
||||
{
|
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/* disable I/D cache */
|
||||
mmu_disable_dcache();
|
||||
mmu_disable_icache();
|
||||
mmu_disable();
|
||||
mmu_invalidate_tlb();
|
||||
|
||||
/* clear pgd and pte table */
|
||||
rt_memset((void *)_pgd_table, 0, 16*1024);
|
||||
rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
|
||||
build_pte_mem_desc(mdesc, size);
|
||||
/* set page table */
|
||||
for (; size > 0; size--)
|
||||
{
|
||||
if (mdesc->mapped_mode == SECT_MAPPED)
|
||||
{
|
||||
mmu_create_pgd(mdesc);
|
||||
}
|
||||
else
|
||||
{
|
||||
mmu_create_pte(mdesc);
|
||||
}
|
||||
|
||||
mdesc++;
|
||||
}
|
||||
|
||||
/* set MMU table address */
|
||||
mmu_setttbase((rt_uint32_t)_pgd_table);
|
||||
|
||||
/* enables MMU */
|
||||
mmu_enable();
|
||||
|
||||
/* enable Instruction Cache */
|
||||
mmu_enable_icache();
|
||||
|
||||
/* enable Data Cache */
|
||||
mmu_enable_dcache();
|
||||
|
||||
mmu_invalidate_icache();
|
||||
mmu_invalidate_dcache_all();
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user