移植到stm32f1，实现手动线赋码控制器功能

2023-09-09 17:27:06 +08:00
parent 8d779a68f3
commit 7baa63de05
382 changed files with 36618 additions and 148064 deletions
--- a/source/rt_thread/libcpu/arm/cortex-m3/context_rvds.S
+++ b/source/rt_thread/libcpu/arm/cortex-m3/context_rvds.S
@@ -181,6 +181,7 @@ rt_hw_interrupt_thread_switch PROC
 HardFault_Handler    PROC

    ; get current context
+    B       .
    TST     lr, #0x04               ; if(!EXC_RETURN[2])
    ITE     EQ
    MRSEQ   r0, msp                 ; [2]=0 ==> Z=1, get fault context from handler.
--- a/source/rt_thread/libcpu/arm/cortex-m7/cpu_cache.c
+++ b/source/rt_thread/libcpu/arm/cortex-m7/cpu_cache.c
@@ -13,7 +13,7 @@
 #include <rtdef.h>
 #include <board.h>

-/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
+/* The L1-caches on all Cortex庐-M7s are divided into lines of 32 bytes. */
 #define L1CACHE_LINESIZE_BYTE       (32)

 void rt_hw_cpu_icache_enable(void)