97 lines
3.7 KiB
C
97 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2014-11-07 weety first version
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*/
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#ifndef __VFP_H__
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#define __VFP_H__
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/* FPSID register bits */
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#define FPSID_IMPLEMENTER_BIT (24)
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#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
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#define FPSID_SW (1 << 23)
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#define FPSID_FORMAT_BIT (21)
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#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
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#define FPSID_NODOUBLE (1 << 20)
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#define FPSID_ARCH_BIT (16)
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#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
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#define FPSID_PART_BIT (8)
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#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
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#define FPSID_VARIANT_BIT (4)
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#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
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#define FPSID_REVISION_BIT (0)
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#define FPSID_REVISION_MASK (0xF << FPSID_REVISION_BIT)
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/* FPSCR register bits */
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#define FPSCR_DN (1<<25) /* Default NaN mode enable bit */
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#define FPSCR_FZ (1<<24) /* Flush-to-zero mode enable bit */
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#define FPSCR_RN (0<<22) /* Round to nearest (RN) mode */
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#define FPSCR_RP (1<<22) /* Round towards plus infinity (RP) mode */
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#define FPSCR_RM (2<<22) /* Round towards minus infinity (RM) mode */
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#define FPSCR_RZ (3<<22) /* Round towards zero (RZ) mode */
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#define FPSCR_RMODE_BIT (22)
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#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
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#define FPSCR_STRIDE_BIT (20)
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#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
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#define FPSCR_LENGTH_BIT (16)
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#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
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#define FPSCR_IDE (1<<15) /* Input Subnormal exception trap enable bit */
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#define FPSCR_IXE (1<<12) /* Inexact exception trap enable bit */
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#define FPSCR_UFE (1<<11) /* Underflow exception trap enable bit */
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#define FPSCR_OFE (1<<10) /* Overflow exception trap enable bit */
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#define FPSCR_DZE (1<<9) /* Division by Zero exception trap enable bit */
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#define FPSCR_IOE (1<<8) /* Invalid Operation exception trap enable bit */
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#define FPSCR_IDC (1<<7) /* Input Subnormal cumulative exception flag */
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#define FPSCR_IXC (1<<4) /* Inexact cumulative exception flag */
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#define FPSCR_UFC (1<<3) /* Underflow cumulative exception flag */
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#define FPSCR_OFC (1<<2) /* Overflow cumulative exception flag */
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#define FPSCR_DZC (1<<1) /* Division by Zero cumulative exception flag */
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#define FPSCR_IOC (1<<0) /* Invalid Operation cumulative exception flag */
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/* FPEXC register bits */
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#define FPEXC_EX (1 << 31) /* When EX is set, the VFP coprocessor is in the exceptional state */
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#define FPEXC_EN (1 << 30) /* VFP enable bit */
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#define FPEXC_DEX (1 << 29) /* Defined synchronous instruction exceptional flag */
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#define FPEXC_FP2V (1 << 28) /* FPINST2 instruction valid flag */
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#define FPEXC_LENGTH_BIT (8)
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#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
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#define FPEXC_INV (1 << 7) /* Input exception flag */
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#define FPEXC_UFC (1 << 3) /* Potential underflow flag */
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#define FPEXC_OFC (1 << 2) /* Potential overflow flag */
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#define FPEXC_IOC (1 << 0) /* Potential invalid operation flag */
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#define FPEXC_TRAP_MASK (FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC)
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/* MVFR0 register bits */
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#define MVFR0_A_SIMD_BIT (0)
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#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
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/* thread switch micro */
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#define THREAD_INIT 0
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#define THREAD_EXIT 1
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/*
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* get VFP register
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*/
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#define vmrs(vfp) ({ \
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rt_uint32_t var; \
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asm("vmrs %0, "#vfp"" : "=r" (var) : : "cc"); \
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var; \
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})
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#define vmsr(vfp, var) \
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asm("vmsr "#vfp", %0" \
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: : "r" (var) : "cc")
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#endif
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