1131 lines
46 KiB
C
1131 lines
46 KiB
C
/**
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******************************************************************************
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* @file system_stm32f4xx.c
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* @author MCD Application Team
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* @version V1.4.0
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* @date 04-August-2014
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F4xx devices.
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (16 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
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* function will do nothing and HSI still used as system clock source. User can
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* add some code to deal with this issue inside the SetSysClock() function.
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*
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* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
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* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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*=============================================================================
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* Supported STM32F40xxx/41xxx devices
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 168000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 168000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 4
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 25000000
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*-----------------------------------------------------------------------------
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* PLL_M | 25
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*-----------------------------------------------------------------------------
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* PLL_N | 336
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*-----------------------------------------------------------------------------
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* PLL_P | 2
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*-----------------------------------------------------------------------------
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* PLL_Q | 7
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Main regulator output voltage | Scale1 mode
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 5
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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*=============================================================================
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* Supported STM32F42xxx/43xxx devices
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 180000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 180000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 4
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 25000000
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*-----------------------------------------------------------------------------
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* PLL_M | 25
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*-----------------------------------------------------------------------------
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* PLL_N | 360
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*-----------------------------------------------------------------------------
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* PLL_P | 2
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*-----------------------------------------------------------------------------
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* PLL_Q | 7
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Main regulator output voltage | Scale1 mode
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 5
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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*=============================================================================
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* Supported STM32F401xx devices
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 84000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 84000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 2
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSE Frequency(Hz) | 25000000
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*-----------------------------------------------------------------------------
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* PLL_M | 25
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*-----------------------------------------------------------------------------
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* PLL_N | 336
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*-----------------------------------------------------------------------------
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* PLL_P | 4
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*-----------------------------------------------------------------------------
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* PLL_Q | 7
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Main regulator output voltage | Scale1 mode
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 2
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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*=============================================================================
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* Supported STM32F411xx devices
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*-----------------------------------------------------------------------------
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* System Clock source | PLL (HSI)
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 100000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 100000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 2
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSI Frequency(Hz) | 16000000
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*-----------------------------------------------------------------------------
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* PLL_M | 16
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*-----------------------------------------------------------------------------
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* PLL_N | 400
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*-----------------------------------------------------------------------------
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* PLL_P | 4
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*-----------------------------------------------------------------------------
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* PLL_Q | 7
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*-----------------------------------------------------------------------------
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* PLLI2S_N | NA
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*-----------------------------------------------------------------------------
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* PLLI2S_R | NA
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*-----------------------------------------------------------------------------
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* I2S input clock | NA
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*-----------------------------------------------------------------------------
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* VDD(V) | 3.3
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*-----------------------------------------------------------------------------
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* Main regulator output voltage | Scale1 mode
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*-----------------------------------------------------------------------------
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* Flash Latency(WS) | 3
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*-----------------------------------------------------------------------------
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* Prefetch Buffer | ON
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*-----------------------------------------------------------------------------
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* Instruction cache | ON
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*-----------------------------------------------------------------------------
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* Data cache | ON
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB OTG FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f4xx_system
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* @{
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*/
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/** @addtogroup STM32F4xx_System_Private_Includes
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* @{
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*/
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#include "stm32f4xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */
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#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
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/* #define DATA_IN_ExtSRAM */
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#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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/* #define DATA_IN_ExtSDRAM */
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#endif /* STM32F427_437x || STM32F429_439xx */
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#if defined (STM32F411xE)
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/*!< Uncomment the following line if you need to clock the STM32F411xE by HSE Bypass
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through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
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and is fixed at 8 MHz.
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Hardware configuration needed for Nucleo Board:
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?SB54, SB55 OFF
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?R35 removed
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?SB16, SB50 ON */
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/* #define USE_HSE_BYPASS */
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#if defined (USE_HSE_BYPASS)
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#define HSE_BYPASS_INPUT_FREQUENCY 8000000
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F411xE */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/************************* PLL Parameters *************************************/
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#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
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#define PLL_M 8
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#else /* STM32F411xE */
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#if defined (USE_HSE_BYPASS)
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#define PLL_M 8
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#else /* STM32F411xE */
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#define PLL_M 16
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#endif /* USE_HSE_BYPASS */
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#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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#if defined (STM32F40_41xxx)
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#define PLL_N 336
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 2
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#endif /* STM32F40_41xxx */
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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#define PLL_N 360
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 2
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#endif /* STM32F427_437x || STM32F429_439xx */
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#if defined (STM32F401xx)
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#define PLL_N 336
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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#endif /* STM32F401xx */
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#if defined (STM32F411xE)
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#define PLL_N 400
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/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P 4
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#endif /* STM32F411xx */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Variables
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* @{
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*/
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#if defined (STM32F40_41xxx)
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uint32_t SystemCoreClock = 168000000;
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#endif /* STM32F40_41xxx */
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#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
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uint32_t SystemCoreClock = 180000000;
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#endif /* STM32F427_437x || STM32F429_439xx */
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#if defined (STM32F401xx)
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uint32_t SystemCoreClock = 84000000;
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#endif /* STM32F401xx */
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#if defined (STM32F411xE)
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uint32_t SystemCoreClock = 100000000;
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#endif /* STM32F401xx */
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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* @{
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*/
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static void SetSysClock(void);
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the System clock source, PLL Multiplier and Divider factors,
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AHB/APBx prescalers and Flash settings ----------------------------------*/
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SetSysClock();
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
|
}
|
|
#elif defined (STM32F411xE)
|
|
#if defined (USE_HSE_BYPASS)
|
|
if (pllsource != 0)
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
|
}
|
|
#else
|
|
if (pllsource == 0)
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
|
}
|
|
#endif /* USE_HSE_BYPASS */
|
|
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
|
|
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
|
SystemCoreClock = pllvco/pllp;
|
|
break;
|
|
default:
|
|
SystemCoreClock = HSI_VALUE;
|
|
break;
|
|
}
|
|
/* Compute HCLK frequency --------------------------------------------------*/
|
|
/* Get HCLK prescaler */
|
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
|
/* HCLK frequency */
|
|
SystemCoreClock >>= tmp;
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
|
* AHB/APBx prescalers and Flash settings
|
|
* @Note This function should be called only once the RCC clock configuration
|
|
* is reset to the default reset state (done in SystemInit() function).
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void SetSysClock(void)
|
|
{
|
|
#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx)
|
|
/******************************************************************************/
|
|
/* PLL (clocked by HSE) used as System clock source */
|
|
/******************************************************************************/
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* Enable HSE */
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do
|
|
{
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
StartUpCounter++;
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
{
|
|
HSEStatus = (uint32_t)0x01;
|
|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* Select regulator voltage output Scale 1 mode */
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
PWR->CR |= PWR_CR_VOS;
|
|
|
|
/* HCLK = SYSCLK / 1*/
|
|
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
|
|
|
#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)
|
|
/* PCLK2 = HCLK / 2*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
|
|
|
/* PCLK1 = HCLK / 4*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
|
#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */
|
|
|
|
#if defined (STM32F401xx)
|
|
/* PCLK2 = HCLK / 2*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
|
|
|
|
/* PCLK1 = HCLK / 4*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
#endif /* STM32F401xx */
|
|
|
|
/* Configure the main PLL */
|
|
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
|
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
|
|
|
/* Enable the main PLL */
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
|
/* Wait till the main PLL is ready */
|
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
{
|
|
}
|
|
|
|
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
|
|
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
|
PWR->CR |= PWR_CR_ODEN;
|
|
while((PWR->CSR & PWR_CSR_ODRDY) == 0)
|
|
{
|
|
}
|
|
PWR->CR |= PWR_CR_ODSWEN;
|
|
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
|
|
{
|
|
}
|
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
|
#endif /* STM32F427_437x || STM32F429_439xx */
|
|
|
|
#if defined (STM32F40_41xxx)
|
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
|
#endif /* STM32F40_41xxx */
|
|
|
|
#if defined (STM32F401xx)
|
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
|
|
#endif /* STM32F401xx */
|
|
|
|
/* Select the main PLL as system clock source */
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
|
/* Wait till the main PLL is used as system clock source */
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock
|
|
configuration. User can add here some code to deal with this error */
|
|
}
|
|
#elif defined (STM32F411xE)
|
|
#if defined (USE_HSE_BYPASS)
|
|
/******************************************************************************/
|
|
/* PLL (clocked by HSE) used as System clock source */
|
|
/******************************************************************************/
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
/* Enable HSE and HSE BYPASS */
|
|
RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do
|
|
{
|
|
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
|
StartUpCounter++;
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
|
{
|
|
HSEStatus = (uint32_t)0x01;
|
|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* Select regulator voltage output Scale 1 mode */
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
PWR->CR |= PWR_CR_VOS;
|
|
|
|
/* HCLK = SYSCLK / 1*/
|
|
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
|
|
|
/* PCLK2 = HCLK / 2*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
|
|
|
|
/* PCLK1 = HCLK / 4*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
|
|
/* Configure the main PLL */
|
|
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
|
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
|
|
|
/* Enable the main PLL */
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
|
/* Wait till the main PLL is ready */
|
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
{
|
|
}
|
|
|
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
|
|
|
|
/* Select the main PLL as system clock source */
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
|
/* Wait till the main PLL is used as system clock source */
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{ /* If HSE fails to start-up, the application will have wrong clock
|
|
configuration. User can add here some code to deal with this error */
|
|
}
|
|
#else /* HSI will be used as PLL clock source */
|
|
/* Select regulator voltage output Scale 1 mode */
|
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
|
PWR->CR |= PWR_CR_VOS;
|
|
|
|
/* HCLK = SYSCLK / 1*/
|
|
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
|
|
|
/* PCLK2 = HCLK / 2*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
|
|
|
|
/* PCLK1 = HCLK / 4*/
|
|
RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
|
|
|
|
/* Configure the main PLL */
|
|
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
|
|
|
|
/* Enable the main PLL */
|
|
RCC->CR |= RCC_CR_PLLON;
|
|
|
|
/* Wait till the main PLL is ready */
|
|
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
|
{
|
|
}
|
|
|
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
|
|
|
|
/* Select the main PLL as system clock source */
|
|
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
|
|
|
/* Wait till the main PLL is used as system clock source */
|
|
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
|
{
|
|
}
|
|
#endif /* USE_HSE_BYPASS */
|
|
#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx */
|
|
}
|
|
|
|
/**
|
|
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
|
* before jump to __main
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
#ifdef DATA_IN_ExtSRAM
|
|
/**
|
|
* @brief Setup the external memory controller.
|
|
* Called in startup_stm32f4xx.s before jump to main.
|
|
* This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
|
|
* This SRAM will be used as program data memory (including heap and stack).
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit_ExtMemCtl(void)
|
|
{
|
|
/*-- GPIOs Configuration -----------------------------------------------------*/
|
|
/*
|
|
+-------------------+--------------------+------------------+--------------+
|
|
+ SRAM pins assignment +
|
|
+-------------------+--------------------+------------------+--------------+
|
|
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
|
|
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
|
|
| PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 |
|
|
| PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 |
|
|
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 |
|
|
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 |
|
|
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
|
|
| PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+
|
|
| PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 |
|
|
| PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 |
|
|
| PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+
|
|
| PD15 <-> FMC_D1 | PE14 <-> FMC_D11 |
|
|
| | PE15 <-> FMC_D12 |
|
|
+------------------+------------------+
|
|
*/
|
|
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
|
RCC->AHB1ENR |= 0x00000078;
|
|
|
|
/* Connect PDx pins to FMC Alternate function */
|
|
GPIOD->AFR[0] = 0x00cc00cc;
|
|
GPIOD->AFR[1] = 0xcccccccc;
|
|
/* Configure PDx pins in Alternate function mode */
|
|
GPIOD->MODER = 0xaaaa0a0a;
|
|
/* Configure PDx pins speed to 100 MHz */
|
|
GPIOD->OSPEEDR = 0xffff0f0f;
|
|
/* Configure PDx pins Output type to push-pull */
|
|
GPIOD->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PDx pins */
|
|
GPIOD->PUPDR = 0x00000000;
|
|
|
|
/* Connect PEx pins to FMC Alternate function */
|
|
GPIOE->AFR[0] = 0xcccccccc;
|
|
GPIOE->AFR[1] = 0xcccccccc;
|
|
/* Configure PEx pins in Alternate function mode */
|
|
GPIOE->MODER = 0xaaaaaaaa;
|
|
/* Configure PEx pins speed to 100 MHz */
|
|
GPIOE->OSPEEDR = 0xffffffff;
|
|
/* Configure PEx pins Output type to push-pull */
|
|
GPIOE->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PEx pins */
|
|
GPIOE->PUPDR = 0x00000000;
|
|
|
|
/* Connect PFx pins to FMC Alternate function */
|
|
GPIOF->AFR[0] = 0x00cccccc;
|
|
GPIOF->AFR[1] = 0xcccc0000;
|
|
/* Configure PFx pins in Alternate function mode */
|
|
GPIOF->MODER = 0xaa000aaa;
|
|
/* Configure PFx pins speed to 100 MHz */
|
|
GPIOF->OSPEEDR = 0xff000fff;
|
|
/* Configure PFx pins Output type to push-pull */
|
|
GPIOF->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PFx pins */
|
|
GPIOF->PUPDR = 0x00000000;
|
|
|
|
/* Connect PGx pins to FMC Alternate function */
|
|
GPIOG->AFR[0] = 0x00cccccc;
|
|
GPIOG->AFR[1] = 0x000000c0;
|
|
/* Configure PGx pins in Alternate function mode */
|
|
GPIOG->MODER = 0x00080aaa;
|
|
/* Configure PGx pins speed to 100 MHz */
|
|
GPIOG->OSPEEDR = 0x000c0fff;
|
|
/* Configure PGx pins Output type to push-pull */
|
|
GPIOG->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PGx pins */
|
|
GPIOG->PUPDR = 0x00000000;
|
|
|
|
/*-- FMC Configuration ------------------------------------------------------*/
|
|
/* Enable the FMC/FSMC interface clock */
|
|
RCC->AHB3ENR |= 0x00000001;
|
|
|
|
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
|
|
/* Configure and enable Bank1_SRAM2 */
|
|
FMC_Bank1->BTCR[2] = 0x00001011;
|
|
FMC_Bank1->BTCR[3] = 0x00000201;
|
|
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
#endif /* STM32F427_437xx || STM32F429_439xx */
|
|
|
|
#if defined (STM32F40_41xxx)
|
|
/* Configure and enable Bank1_SRAM2 */
|
|
FSMC_Bank1->BTCR[2] = 0x00001011;
|
|
FSMC_Bank1->BTCR[3] = 0x00000201;
|
|
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
|
#endif /* STM32F40_41xxx */
|
|
|
|
/*
|
|
Bank1_SRAM2 is configured as follow:
|
|
In case of FSMC configuration
|
|
NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
|
|
NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
|
|
NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
|
|
NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
|
|
NORSRAMTimingStructure.FSMC_CLKDivision = 0;
|
|
NORSRAMTimingStructure.FSMC_DataLatency = 0;
|
|
NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
|
|
|
|
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
|
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
|
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
|
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
|
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
|
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
|
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
|
|
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
|
|
|
|
In case of FMC configuration
|
|
NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
|
|
NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
|
|
NORSRAMTimingStructure.FMC_DataSetupTime = 2;
|
|
NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
|
|
NORSRAMTimingStructure.FMC_CLKDivision = 0;
|
|
NORSRAMTimingStructure.FMC_DataLatency = 0;
|
|
NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
|
|
|
|
FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
|
|
FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
|
|
FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
|
|
FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
|
|
FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
|
|
FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
|
|
FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
|
|
FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
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FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
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FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
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*/
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|
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}
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#endif /* DATA_IN_ExtSRAM */
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#ifdef DATA_IN_ExtSDRAM
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f4xx.s before jump to main.
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* This function configures the external SDRAM mounted on STM324x9I_EVAL board
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* This SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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|
*/
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void SystemInit_ExtMemCtl(void)
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{
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register uint32_t index;
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|
|
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/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
|
clock */
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RCC->AHB1ENR |= 0x000001FC;
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|
|
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/* Connect PCx pins to FMC Alternate function */
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GPIOC->AFR[0] = 0x0000000c;
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GPIOC->AFR[1] = 0x00007700;
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/* Configure PCx pins in Alternate function mode */
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GPIOC->MODER = 0x00a00002;
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/* Configure PCx pins speed to 50 MHz */
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GPIOC->OSPEEDR = 0x00a00002;
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/* Configure PCx pins Output type to push-pull */
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GPIOC->OTYPER = 0x00000000;
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|
/* No pull-up, pull-down for PCx pins */
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GPIOC->PUPDR = 0x00500000;
|
|
|
|
/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
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|
GPIOD->MODER = 0xA02A000A;
|
|
/* Configure PDx pins speed to 50 MHz */
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|
GPIOD->OSPEEDR = 0xA02A000A;
|
|
/* Configure PDx pins Output type to push-pull */
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|
GPIOD->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PDx pins */
|
|
GPIOD->PUPDR = 0x00000000;
|
|
|
|
/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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|
/* Configure PEx pins in Alternate function mode */
|
|
GPIOE->MODER = 0xAAAA800A;
|
|
/* Configure PEx pins speed to 50 MHz */
|
|
GPIOE->OSPEEDR = 0xAAAA800A;
|
|
/* Configure PEx pins Output type to push-pull */
|
|
GPIOE->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PEx pins */
|
|
GPIOE->PUPDR = 0x00000000;
|
|
|
|
/* Connect PFx pins to FMC Alternate function */
|
|
GPIOF->AFR[0] = 0xcccccccc;
|
|
GPIOF->AFR[1] = 0xcccccccc;
|
|
/* Configure PFx pins in Alternate function mode */
|
|
GPIOF->MODER = 0xAA800AAA;
|
|
/* Configure PFx pins speed to 50 MHz */
|
|
GPIOF->OSPEEDR = 0xAA800AAA;
|
|
/* Configure PFx pins Output type to push-pull */
|
|
GPIOF->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PFx pins */
|
|
GPIOF->PUPDR = 0x00000000;
|
|
|
|
/* Connect PGx pins to FMC Alternate function */
|
|
GPIOG->AFR[0] = 0xcccccccc;
|
|
GPIOG->AFR[1] = 0xcccccccc;
|
|
/* Configure PGx pins in Alternate function mode */
|
|
GPIOG->MODER = 0xaaaaaaaa;
|
|
/* Configure PGx pins speed to 50 MHz */
|
|
GPIOG->OSPEEDR = 0xaaaaaaaa;
|
|
/* Configure PGx pins Output type to push-pull */
|
|
GPIOG->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PGx pins */
|
|
GPIOG->PUPDR = 0x00000000;
|
|
|
|
/* Connect PHx pins to FMC Alternate function */
|
|
GPIOH->AFR[0] = 0x00C0CC00;
|
|
GPIOH->AFR[1] = 0xCCCCCCCC;
|
|
/* Configure PHx pins in Alternate function mode */
|
|
GPIOH->MODER = 0xAAAA08A0;
|
|
/* Configure PHx pins speed to 50 MHz */
|
|
GPIOH->OSPEEDR = 0xAAAA08A0;
|
|
/* Configure PHx pins Output type to push-pull */
|
|
GPIOH->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PHx pins */
|
|
GPIOH->PUPDR = 0x00000000;
|
|
|
|
/* Connect PIx pins to FMC Alternate function */
|
|
GPIOI->AFR[0] = 0xCCCCCCCC;
|
|
GPIOI->AFR[1] = 0x00000CC0;
|
|
/* Configure PIx pins in Alternate function mode */
|
|
GPIOI->MODER = 0x0028AAAA;
|
|
/* Configure PIx pins speed to 50 MHz */
|
|
GPIOI->OSPEEDR = 0x0028AAAA;
|
|
/* Configure PIx pins Output type to push-pull */
|
|
GPIOI->OTYPER = 0x00000000;
|
|
/* No pull-up, pull-down for PIx pins */
|
|
GPIOI->PUPDR = 0x00000000;
|
|
|
|
/*-- FMC Configuration ------------------------------------------------------*/
|
|
/* Enable the FMC interface clock */
|
|
RCC->AHB3ENR |= 0x00000001;
|
|
|
|
/* Configure and enable SDRAM bank1 */
|
|
FMC_Bank5_6->SDCR[0] = 0x000039D0;
|
|
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
|
|
|
/* SDRAM initialization sequence */
|
|
/* Clock enable command */
|
|
FMC_Bank5_6->SDCMR = 0x00000011;
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
while((tmpreg != 0) & (timeout-- > 0))
|
|
{
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
}
|
|
|
|
/* Delay */
|
|
for (index = 0; index<1000; index++);
|
|
|
|
/* PALL command */
|
|
FMC_Bank5_6->SDCMR = 0x00000012;
|
|
timeout = 0xFFFF;
|
|
while((tmpreg != 0) & (timeout-- > 0))
|
|
{
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
}
|
|
|
|
/* Auto refresh command */
|
|
FMC_Bank5_6->SDCMR = 0x00000073;
|
|
timeout = 0xFFFF;
|
|
while((tmpreg != 0) & (timeout-- > 0))
|
|
{
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
}
|
|
|
|
/* MRD register program */
|
|
FMC_Bank5_6->SDCMR = 0x00046014;
|
|
timeout = 0xFFFF;
|
|
while((tmpreg != 0) & (timeout-- > 0))
|
|
{
|
|
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
|
}
|
|
|
|
/* Set refresh count */
|
|
tmpreg = FMC_Bank5_6->SDRTR;
|
|
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
|
|
|
|
/* Disable write protection */
|
|
tmpreg = FMC_Bank5_6->SDCR[0];
|
|
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
|
|
|
/*
|
|
Bank1_SDRAM is configured as follow:
|
|
|
|
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
|
|
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
|
|
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
|
|
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
|
|
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
|
|
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
|
|
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
|
|
|
|
FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
|
|
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
|
|
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
|
|
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
|
|
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
|
|
FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
|
|
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
|
|
FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
|
|
FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
|
|
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
|
|
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
|
|
*/
|
|
|
|
}
|
|
#endif /* DATA_IN_ExtSDRAM */
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|