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elec_capture/source/nand/nand.h

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实现读取nand的id，正在编写坏块管理算法
2023-06-12 18:32:55 +08:00
#ifndef _NAND_H
#define _NAND_H
#include "stm32h7xx_hal.h"
//////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>ѧϰʹ<CFB0>ã<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κ<EFBFBD><CEBA><EFBFBD>;
//ALIENTEK STM32H7<48><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//NAND<4E><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ԭ<EFBFBD><D4AD>@ALIENTEK
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̳:www.openedv.com
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:2017/8/16
//<2F>汾<EFBFBD><E6B1BE>V1.0
//<2F><>Ȩ<EFBFBD><C8A8><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؾ<EFBFBD><D8BE><EFBFBD>
//Copyright(C) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿƼ<D3BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾ 2014-2024
//All rights reserved
//////////////////////////////////////////////////////////////////////////////////
//<2F><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5>
//V1.1 20160520
//1,<2C><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>ECC֧<43><D6A7>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NAND_ECC_SECTOR_SIZE<5A><45>СΪ<D0A1><CEAA>λ<EFBFBD><CEBB><EFBFBD>ж<EFBFBD>дʱ<D0B4><CAB1><EFBFBD><EFBFBD>)
//2,<2C><><EFBFBD><EFBFBD>NAND_Delay<61><79><EFBFBD><EFBFBD>,<2C><><EFBFBD>ڵȴ<DAB5>tADL/tWHR
//3,<2C><><EFBFBD><EFBFBD>NAND_WritePageConst<73><74><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѱ<EFBFBD><D1B0><EFBFBD><EFBFBD>.
//V1.2 20160525
//1,ȥ<><C8A5>NAND_SEC_SIZE<5A>궨<EFBFBD>壬<EFBFBD><E5A3AC>NAND_ECC_SECTOR_SIZE<5A><45><EFBFBD><EFBFBD>
//2,ȥ<><C8A5>nand_dev<65>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>secbufָ<66>룬<EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
//////////////////////////////////////////////////////////////////////////////////
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32;
typedef const int16_t sc16;
typedef const int8_t sc8;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32;
typedef __I int16_t vsc16;
typedef __I int8_t vsc8;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32;
typedef const uint16_t uc16;
typedef const uint8_t uc8;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32;
typedef __I uint16_t vuc16;
typedef __I uint8_t vuc8;
#define NAND_MAX_PAGE_SIZE 4096 //<2F><><EFBFBD><EFBFBD>NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PAGE<47><45>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPARE<52><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>4096<39>ֽ<EFBFBD>
#define NAND_ECC_SECTOR_SIZE 512 //ִ<><D6B4>ECC<43><43><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>Ԫ<EFBFBD><D4AA>С<EFBFBD><D0A1>Ĭ<EFBFBD><C4AC>512<31>ֽ<EFBFBD>
//NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
#define NAND_TADL_DELAY 35 //tADL<44>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>70ns
#define NAND_TWHR_DELAY 30 //tWHR<48>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>60ns
#define NAND_TRHW_DELAY 50 //tRHW<48>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>100ns
#define NAND_TPROG_DELAY 350 //tPROG<4F>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ֵ200us,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ700us
#define NAND_TBERS_DELAY 4 //tBERS<52>ȴ<EFBFBD><C8B4>ӳ<EFBFBD>,<2C><><EFBFBD><EFBFBD>ֵ3.5ms,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ10ms
#define NAND_TRST_FIRST_DELAY 3 //tRST<53><54>λ<EFBFBD><CEBB><EFBFBD>ĵ<EFBFBD>һ<EFBFBD>εȴ<CEB5>ʱ<EFBFBD>䣬<EFBFBD><E4A3AC><EFBFBD><EFBFBD>Ϊ3ms
//NAND<4E><44><EFBFBD>Խṹ<D4BD><E1B9B9>
typedef struct
{
u16 page_totalsize; //ÿҳ<C3BF>ܴ<EFBFBD>С<EFBFBD><D0A1>main<69><6E><EFBFBD><EFBFBD>spare<72><65><EFBFBD>ܺ<EFBFBD>
u16 page_mainsize; //ÿҳ<C3BF><D2B3>main<69><6E><EFBFBD><EFBFBD>С
u16 page_sparesize; //ÿҳ<C3BF><D2B3>spare<72><65><EFBFBD><EFBFBD>С
u8 block_pagenum; //ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>
u16 plane_blocknum; //ÿ<><C3BF>plane<6E><65><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD>
u16 block_totalnum; //<2F>ܵĿ<DCB5><C4BF><EFBFBD><EFBFBD><EFBFBD>
u16 good_blocknum; //<2F>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD>
u16 valid_blocknum; //<2F><>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD>ļ<EFBFBD>ϵͳʹ<CDB3>õĺÿ<C4BA><C3BF><EFBFBD><EFBFBD><EFBFBD>)
u32 id; //NAND FLASH ID
u16 *lut; //LUT<55><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD>-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>
u32 ecc_hard; //Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ECCֵ
u32 ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECCӲ<43><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
u32 ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECC<43><43>ȡ<EFBFBD><C8A1>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}nand_attriute;
extern nand_attriute nand_dev; //nand<6E><64>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9>
#define NAND_RB HAL_GPIO_ReadPin(GPIOD,GPIO_PIN_6)//NAND Flash<73><68><EFBFBD><EFBFBD>/æ<><C3A6><EFBFBD><EFBFBD>
#define NAND_ADDRESS 0X80000000 //nand flash<73>ķ<EFBFBD><C4B7>ʵ<EFBFBD>ַ,<2C><>NCE3,<2C><>ַΪ:0X8000 0000
#define NAND_CMD 1<<16 //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define NAND_ADDR 1<<17 //<2F><><EFBFBD>͵<EFBFBD>ַ
//NAND FLASH<53><48><EFBFBD><EFBFBD>
#define NAND_READID 0X90 //<2F><>IDָ<44><D6B8>
#define NAND_FEATURE 0XEF //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
#define NAND_RESET 0XFF //<2F><>λNAND
#define NAND_READSTA 0X70 //<2F><>״̬
#define NAND_AREA_A 0X00
#define NAND_AREA_TRUE1 0X30
#define NAND_WRITE0 0X80
#define NAND_WRITE_TURE1 0X10
#define NAND_ERASE0 0X60
#define NAND_ERASE1 0XD0
#define NAND_MOVEDATA_CMD0 0X00
#define NAND_MOVEDATA_CMD1 0X35
#define NAND_MOVEDATA_CMD2 0X85
#define NAND_MOVEDATA_CMD3 0X10
//NAND FLASH״̬
#define NSTA_READY 0X40 //nand<6E>Ѿ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>
#define NSTA_ERROR 0X01 //nand<6E><64><EFBFBD><EFBFBD>
#define NSTA_TIMEOUT 0X02 //<2F><>ʱ
#define NSTA_ECC1BITERR 0X03 //ECC 1bit<69><74><EFBFBD><EFBFBD>
#define NSTA_ECC2BITERR 0X04 //ECC 2bit<69><74><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD>
//NAND FLASH<53>ͺźͶ<C5BA>Ӧ<EFBFBD><D3A6>ID<49><44>
#define MT29F4G08ABADA 0XDC909556 //MT29F4G08ABADA
#define MT29F16G08ABABA 0X48002689 //MT29F16G08ABABA
//MPU<50><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define NAND_REGION_NUMBER MPU_REGION_NUMBER4 //NAND FLASHʹ<48><CAB9>region4
#define NAND_ADDRESS_START 0X80000000 //NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD>׵<EFBFBD>ַ
#define NAND_REGION_SIZE MPU_REGION_SIZE_256MB //NAND FLASH<53><48><EFBFBD><EFBFBD>С
u8 NAND_Init(void);
u8 NAND_ModeSet(u8 mode);
u32 NAND_ReadID(void);
u8 NAND_ReadStatus(void);
u8 NAND_WaitForReady(void);
u8 NAND_Reset(void);
u8 NAND_WaitRB(vu8 rb);
void NAND_Delay(vu32 i);
void NAND_MPU_Config(void);
u8 NAND_ReadPage(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
u8 NAND_ReadPageComp(u32 PageNum,u16 ColNum,u32 CmpVal,u16 NumByteToRead,u16 *NumByteEqual);
u8 NAND_WritePage(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToWrite);
u8 NAND_WritePageConst(u32 PageNum,u16 ColNum,u32 cval,u16 NumByteToWrite);
u8 NAND_CopyPageWithoutWrite(u32 Source_PageNum,u32 Dest_PageNum);
u8 NAND_CopyPageWithWrite(u32 Source_PageNum,u32 Dest_PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToWrite);
u8 NAND_ReadSpare(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
u8 NAND_WriteSpare(u32 PageNum,u16 ColNum,u8 *pBuffer,u16 NumByteToRead);
u8 NAND_EraseBlock(u32 BlockNum);
void NAND_EraseChip(void);
u16 NAND_ECC_Get_OE(u8 oe,u32 eccval);
u8 NAND_ECC_Correction(u8* data_buf,u32 eccrd,u32 ecccl);
#endif
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