kunlun/inc/hw/reg/riscv/11/rgf_rx.h

//-----------------------------------
#define CFG_TMI0_BAND0_ADDR 0x0000
#define CFG_TMI0_BAND0_PBFL_OFFSET 8
#define CFG_TMI0_BAND0_PBFL_MASK 0x0007FF00
#define CFG_TMI0_BAND0_NUMSYM_OFFSET 0
#define CFG_TMI0_BAND0_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI0_BAND1_ADDR 0x0004
#define CFG_TMI0_BAND1_PBFL_OFFSET 8
#define CFG_TMI0_BAND1_PBFL_MASK 0x0007FF00
#define CFG_TMI0_BAND1_NUMSYM_OFFSET 0
#define CFG_TMI0_BAND1_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI0_BAND2_ADDR 0x0008
#define CFG_TMI0_BAND2_PBFL_OFFSET 8
#define CFG_TMI0_BAND2_PBFL_MASK 0x0007FF00
#define CFG_TMI0_BAND2_NUMSYM_OFFSET 0
#define CFG_TMI0_BAND2_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI0_BAND3_ADDR 0x000C
#define CFG_TMI0_BAND3_PBFL_OFFSET 8
#define CFG_TMI0_BAND3_PBFL_MASK 0x0007FF00
#define CFG_TMI0_BAND3_NUMSYM_OFFSET 0
#define CFG_TMI0_BAND3_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI1_BAND0_ADDR 0x0010
#define CFG_TMI1_BAND0_PBFL_OFFSET 8
#define CFG_TMI1_BAND0_PBFL_MASK 0x0007FF00
#define CFG_TMI1_BAND0_NUMSYM_OFFSET 0
#define CFG_TMI1_BAND0_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI1_BAND1_ADDR 0x0014
#define CFG_TMI1_BAND1_PBFL_OFFSET 8
#define CFG_TMI1_BAND1_PBFL_MASK 0x0007FF00
#define CFG_TMI1_BAND1_NUMSYM_OFFSET 0
#define CFG_TMI1_BAND1_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI1_BAND2_ADDR 0x0018
#define CFG_TMI1_BAND2_PBFL_OFFSET 8
#define CFG_TMI1_BAND2_PBFL_MASK 0x0007FF00
#define CFG_TMI1_BAND2_NUMSYM_OFFSET 0
#define CFG_TMI1_BAND2_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI1_BAND3_ADDR 0x001C
#define CFG_TMI1_BAND3_PBFL_OFFSET 8
#define CFG_TMI1_BAND3_PBFL_MASK 0x0007FF00
#define CFG_TMI1_BAND3_NUMSYM_OFFSET 0
#define CFG_TMI1_BAND3_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI2_BAND0_ADDR 0x0020
#define CFG_TMI2_BAND0_PBFL_OFFSET 8
#define CFG_TMI2_BAND0_PBFL_MASK 0x0007FF00
#define CFG_TMI2_BAND0_NUMSYM_OFFSET 0
#define CFG_TMI2_BAND0_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI2_BAND1_ADDR 0x0024
#define CFG_TMI2_BAND1_PBFL_OFFSET 8
#define CFG_TMI2_BAND1_PBFL_MASK 0x0007FF00
#define CFG_TMI2_BAND1_NUMSYM_OFFSET 0
#define CFG_TMI2_BAND1_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI2_BAND2_ADDR 0x0028
#define CFG_TMI2_BAND2_PBFL_OFFSET 8
#define CFG_TMI2_BAND2_PBFL_MASK 0x0007FF00
#define CFG_TMI2_BAND2_NUMSYM_OFFSET 0
#define CFG_TMI2_BAND2_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI2_BAND3_ADDR 0x002C
#define CFG_TMI2_BAND3_PBFL_OFFSET 8
#define CFG_TMI2_BAND3_PBFL_MASK 0x0007FF00
#define CFG_TMI2_BAND3_NUMSYM_OFFSET 0
#define CFG_TMI2_BAND3_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI3_BAND0_ADDR 0x0030
#define CFG_TMI3_BAND0_PBFL_OFFSET 8
#define CFG_TMI3_BAND0_PBFL_MASK 0x0007FF00
#define CFG_TMI3_BAND0_NUMSYM_OFFSET 0
#define CFG_TMI3_BAND0_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI3_BAND1_ADDR 0x0034
#define CFG_TMI3_BAND1_PBFL_OFFSET 8
#define CFG_TMI3_BAND1_PBFL_MASK 0x0007FF00
#define CFG_TMI3_BAND1_NUMSYM_OFFSET 0
#define CFG_TMI3_BAND1_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI3_BAND2_ADDR 0x0038
#define CFG_TMI3_BAND2_PBFL_OFFSET 8
#define CFG_TMI3_BAND2_PBFL_MASK 0x0007FF00
#define CFG_TMI3_BAND2_NUMSYM_OFFSET 0
#define CFG_TMI3_BAND2_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_TMI3_BAND3_ADDR 0x003C
#define CFG_TMI3_BAND3_PBFL_OFFSET 8
#define CFG_TMI3_BAND3_PBFL_MASK 0x0007FF00
#define CFG_TMI3_BAND3_NUMSYM_OFFSET 0
#define CFG_TMI3_BAND3_NUMSYM_MASK 0x000000FF

//-----------------------------------
#define CFG_RX_FILTER_0_ADDR 0x0040
#define CFG_FC_CRCERR_FILTER_DIS_OFFSET 3
#define CFG_FC_CRCERR_FILTER_DIS_MASK 0x00000008
#define CFG_NID_FILTER_DIS_OFFSET 2
#define CFG_NID_FILTER_DIS_MASK 0x00000004
#define CFG_MPDU_DTEI_FILTER_DIS_OFFSET 1
#define CFG_MPDU_DTEI_FILTER_DIS_MASK 0x00000002
#define CFG_BEACON_PHASE_FILTER_DIS_OFFSET 0
#define CFG_BEACON_PHASE_FILTER_DIS_MASK 0x00000001

//-----------------------------------
#define CFG_RX_FILTER_1_ADDR 0x0078
#define CFG_SG_DT_FILTER_BLACKLIST_0_OFFSET 28
#define CFG_SG_DT_FILTER_BLACKLIST_0_MASK 0xF0000000
#define CFG_SG_DT_FILTER_BLACKLIST_1_OFFSET 24
#define CFG_SG_DT_FILTER_BLACKLIST_1_MASK 0x0F000000
#define CFG_SG_DT_FILTER_BLACKLIST_2_OFFSET 20
#define CFG_SG_DT_FILTER_BLACKLIST_2_MASK 0x00F00000
#define CFG_SG_DT_FILTER_BLACKLIST_3_OFFSET 16
#define CFG_SG_DT_FILTER_BLACKLIST_3_MASK 0x000F0000
#define CFG_GP_DT_FILTER_BLACKLIST_0_OFFSET 12
#define CFG_GP_DT_FILTER_BLACKLIST_0_MASK 0x0000F000
#define CFG_GP_DT_FILTER_BLACKLIST_1_OFFSET 8
#define CFG_GP_DT_FILTER_BLACKLIST_1_MASK 0x00000F00
#define CFG_GP_DT_FILTER_BLACKLIST_2_OFFSET 4
#define CFG_GP_DT_FILTER_BLACKLIST_2_MASK 0x000000F0
#define CFG_GP_DT_FILTER_BLACKLIST_3_OFFSET 0
#define CFG_GP_DT_FILTER_BLACKLIST_3_MASK 0x0000000F

//-----------------------------------
#define CFG_VLAN0_NID_ADDR 0x0044
#define CFG_VLAN0_NID_OFFSET 0
#define CFG_VLAN0_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN1_NID_ADDR 0x0048
#define CFG_VLAN1_NID_OFFSET 0
#define CFG_VLAN1_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN2_NID_ADDR 0x004C
#define CFG_VLAN2_NID_OFFSET 0
#define CFG_VLAN2_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN3_NID_ADDR 0x0050
#define CFG_VLAN3_NID_OFFSET 0
#define CFG_VLAN3_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN4_NID_ADDR 0x0054
#define CFG_VLAN4_NID_OFFSET 0
#define CFG_VLAN4_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN5_NID_ADDR 0x0058
#define CFG_VLAN5_NID_OFFSET 0
#define CFG_VLAN5_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN6_NID_ADDR 0x005C
#define CFG_VLAN6_NID_OFFSET 0
#define CFG_VLAN6_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_VLAN7_NID_ADDR 0x0060
#define CFG_VLAN7_NID_OFFSET 0
#define CFG_VLAN7_NID_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_CTRL_ADDR 0x0064
#define CFG_PB_HDR_TO_BUFFER_OFFSET 31
#define CFG_PB_HDR_TO_BUFFER_MASK 0x80000000
#define CFG_HASH_ENABLE_OFFSET 30
#define CFG_HASH_ENABLE_MASK 0x40000000
#define CFG_RX_FC_CRC_FROM_PHY_OFFSET 29
#define CFG_RX_FC_CRC_FROM_PHY_MASK 0x20000000
#define CFG_RX_PB_CRC_FROM_PHY_OFFSET 28
#define CFG_RX_PB_CRC_FROM_PHY_MASK 0x10000000
#define CFG_RX_GET_FC_FROM_PHY_OFFSET 27
#define CFG_RX_GET_FC_FROM_PHY_MASK 0x08000000
#define CFG_RX_BEACON_PLD_CRC_BY_SW_OFFSET 26
#define CFG_RX_BEACON_PLD_CRC_BY_SW_MASK 0x04000000
#define CFG_DBG_DISABLE_RX_OFFSET 25
#define CFG_DBG_DISABLE_RX_MASK 0x02000000
#define CFG_DBG_DISABLE_RX_VECTOR_OFFSET 24
#define CFG_DBG_DISABLE_RX_VECTOR_MASK 0x01000000
#define CFG_DBG_DISABLE_RX_FC_OFFSET 23
#define CFG_DBG_DISABLE_RX_FC_MASK 0x00800000
#define CFG_DBG_DISABLE_RX_PB_OFFSET 22
#define CFG_DBG_DISABLE_RX_PB_MASK 0x00400000
#define CFG_DBG_DISABLE_RX_ACK_OFFSET 21
#define CFG_DBG_DISABLE_RX_ACK_MASK 0x00200000

//-----------------------------------
#define CFG_BUFFER_RING0_0_ADDR 0x0068
#define CFG_RING0_PTR_OFFSET 0
#define CFG_RING0_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUFFER_RING0_1_ADDR 0x006c
#define CFG_RING0_BUF_SIZE_FILTER_SEL_OFFSET 24
#define CFG_RING0_BUF_SIZE_FILTER_SEL_MASK 0x01000000
#define CFG_RING0_FILTER_OFFSET 20
#define CFG_RING0_FILTER_MASK 0x00F00000
#define CFG_RING0_BUF_SIZE_OFFSET 10
#define CFG_RING0_BUF_SIZE_MASK 0x000FFC00
#define CFG_RING0_BUF_NUM_OFFSET 0
#define CFG_RING0_BUF_NUM_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING0_2_ADDR 0x0070
#define RING0_STATUS_OFFSET 31
#define RING0_STATUS_MASK 0x80000000
#define CFG_RING0_EN_OFFSET 30
#define CFG_RING0_EN_MASK 0x40000000
#define CFG_RING0_LOW_WATERMARK_OFFSET 20
#define CFG_RING0_LOW_WATERMARK_MASK 0x3FF00000
#define RO_RING0_WR_IDX_OFFSET 10
#define RO_RING0_WR_IDX_MASK 0x000FFC00
#define CFG_RING0_RD_IDX_OFFSET 0
#define CFG_RING0_RD_IDX_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING0_3_ADDR 0x0074
#define CFG_RING0_DESC_EN_OFFSET 21
#define CFG_RING0_DESC_EN_MASK 0x00200000
#define CFG_RING0_PAYLOAD_EN_OFFSET 20
#define CFG_RING0_PAYLOAD_EN_MASK 0x00100000
#define CFG_RING0_DESC_OFFSET_OFFSET 10
#define CFG_RING0_DESC_OFFSET_MASK 0x000FFC00
#define CFG_RING0_PAYLOAD_OFFSET_OFFSET 0
#define CFG_RING0_PAYLOAD_OFFSET_MASK 0x000003FF

//-----------------------------------
#define CFG_RESP_CTRL_ADDR 0x007c
#define CFG_HW_RESP_EN_OFFSET 0
#define CFG_HW_RESP_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BUFFER_RING1_0_ADDR 0x0080
#define CFG_RING1_PTR_OFFSET 0
#define CFG_RING1_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUFFER_RING1_1_ADDR 0x0084
#define CFG_RING1_BUF_SIZE_FILTER_SEL_OFFSET 24
#define CFG_RING1_BUF_SIZE_FILTER_SEL_MASK 0x01000000
#define CFG_RING1_FILTER_OFFSET 20
#define CFG_RING1_FILTER_MASK 0x00F00000
#define CFG_RING1_BUF_SIZE_OFFSET 10
#define CFG_RING1_BUF_SIZE_MASK 0x000FFC00
#define CFG_RING1_BUF_NUM_OFFSET 0
#define CFG_RING1_BUF_NUM_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING1_2_ADDR 0x0088
#define RING1_STATUS_OFFSET 31
#define RING1_STATUS_MASK 0x80000000
#define CFG_RING1_EN_OFFSET 30
#define CFG_RING1_EN_MASK 0x40000000
#define CFG_RING1_LOW_WATERMARK_OFFSET 20
#define CFG_RING1_LOW_WATERMARK_MASK 0x3FF00000
#define RO_RING1_WR_IDX_OFFSET 10
#define RO_RING1_WR_IDX_MASK 0x000FFC00
#define CFG_RING1_RD_IDX_OFFSET 0
#define CFG_RING1_RD_IDX_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING1_3_ADDR 0x008c
#define CFG_RING1_DESC_EN_OFFSET 21
#define CFG_RING1_DESC_EN_MASK 0x00200000
#define CFG_RING1_PAYLOAD_EN_OFFSET 20
#define CFG_RING1_PAYLOAD_EN_MASK 0x00100000
#define CFG_RING1_DESC_OFFSET_OFFSET 10
#define CFG_RING1_DESC_OFFSET_MASK 0x000FFC00
#define CFG_RING1_PAYLOAD_OFFSET_OFFSET 0
#define CFG_RING1_PAYLOAD_OFFSET_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING2_0_ADDR 0x0090
#define CFG_RING2_PTR_OFFSET 0
#define CFG_RING2_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUFFER_RING2_1_ADDR 0x0094
#define CFG_RING2_BUF_SIZE_FILTER_SEL_OFFSET 24
#define CFG_RING2_BUF_SIZE_FILTER_SEL_MASK 0x01000000
#define CFG_RING2_FILTER_OFFSET 20
#define CFG_RING2_FILTER_MASK 0x00F00000
#define CFG_RING2_BUF_SIZE_OFFSET 10
#define CFG_RING2_BUF_SIZE_MASK 0x000FFC00
#define CFG_RING2_BUF_NUM_OFFSET 0
#define CFG_RING2_BUF_NUM_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING2_2_ADDR 0x0098
#define RING2_STATUS_OFFSET 31
#define RING2_STATUS_MASK 0x80000000
#define CFG_RING2_EN_OFFSET 30
#define CFG_RING2_EN_MASK 0x40000000
#define CFG_RING2_LOW_WATERMARK_OFFSET 20
#define CFG_RING2_LOW_WATERMARK_MASK 0x3FF00000
#define RO_RING2_WR_IDX_OFFSET 10
#define RO_RING2_WR_IDX_MASK 0x000FFC00
#define CFG_RING2_RD_IDX_OFFSET 0
#define CFG_RING2_RD_IDX_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING2_3_ADDR 0x009c
#define CFG_RING2_DESC_EN_OFFSET 21
#define CFG_RING2_DESC_EN_MASK 0x00200000
#define CFG_RING2_PAYLOAD_EN_OFFSET 20
#define CFG_RING2_PAYLOAD_EN_MASK 0x00100000
#define CFG_RING2_DESC_OFFSET_OFFSET 10
#define CFG_RING2_DESC_OFFSET_MASK 0x000FFC00
#define CFG_RING2_PAYLOAD_OFFSET_OFFSET 0
#define CFG_RING2_PAYLOAD_OFFSET_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING3_0_ADDR 0x00a0
#define CFG_RING3_PTR_OFFSET 0
#define CFG_RING3_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUFFER_RING3_1_ADDR 0x00a4
#define CFG_RING3_BUF_SIZE_FILTER_SEL_OFFSET 24
#define CFG_RING3_BUF_SIZE_FILTER_SEL_MASK 0x01000000
#define CFG_RING3_FILTER_OFFSET 20
#define CFG_RING3_FILTER_MASK 0x00F00000
#define CFG_RING3_BUF_SIZE_OFFSET 10
#define CFG_RING3_BUF_SIZE_MASK 0x000FFC00
#define CFG_RING3_BUF_NUM_OFFSET 0
#define CFG_RING3_BUF_NUM_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING3_2_ADDR 0x00a8
#define RING3_STATUS_OFFSET 31
#define RING3_STATUS_MASK 0x80000000
#define CFG_RING3_EN_OFFSET 30
#define CFG_RING3_EN_MASK 0x40000000
#define CFG_RING3_LOW_WATERMARK_OFFSET 20
#define CFG_RING3_LOW_WATERMARK_MASK 0x3FF00000
#define RO_RING3_WR_IDX_OFFSET 10
#define RO_RING3_WR_IDX_MASK 0x000FFC00
#define CFG_RING3_RD_IDX_OFFSET 0
#define CFG_RING3_RD_IDX_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING3_3_ADDR 0x00ac
#define CFG_RING3_DESC_EN_OFFSET 21
#define CFG_RING3_DESC_EN_MASK 0x00200000
#define CFG_RING3_PAYLOAD_EN_OFFSET 20
#define CFG_RING3_PAYLOAD_EN_MASK 0x00100000
#define CFG_RING3_DESC_OFFSET_OFFSET 10
#define CFG_RING3_DESC_OFFSET_MASK 0x000FFC00
#define CFG_RING3_PAYLOAD_OFFSET_OFFSET 0
#define CFG_RING3_PAYLOAD_OFFSET_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING4_0_ADDR 0x00b0
#define CFG_RING4_PTR_OFFSET 0
#define CFG_RING4_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BUFFER_RING4_1_ADDR 0x00b4
#define CFG_RING4_BUF_SIZE_FILTER_SEL_OFFSET 24
#define CFG_RING4_BUF_SIZE_FILTER_SEL_MASK 0x01000000
#define CFG_RING4_FILTER_OFFSET 20
#define CFG_RING4_FILTER_MASK 0x00F00000
#define CFG_RING4_BUF_SIZE_OFFSET 10
#define CFG_RING4_BUF_SIZE_MASK 0x000FFC00
#define CFG_RING4_BUF_NUM_OFFSET 0
#define CFG_RING4_BUF_NUM_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING4_2_ADDR 0x00b8
#define RING4_STATUS_OFFSET 31
#define RING4_STATUS_MASK 0x80000000
#define CFG_RING4_EN_OFFSET 30
#define CFG_RING4_EN_MASK 0x40000000
#define CFG_RING4_LOW_WATERMARK_OFFSET 20
#define CFG_RING4_LOW_WATERMARK_MASK 0x3FF00000
#define RO_RING4_WR_IDX_OFFSET 10
#define RO_RING4_WR_IDX_MASK 0x000FFC00
#define CFG_RING4_RD_IDX_OFFSET 0
#define CFG_RING4_RD_IDX_MASK 0x000003FF

//-----------------------------------
#define CFG_BUFFER_RING4_3_ADDR 0x00bc
#define CFG_RING4_DESC_EN_OFFSET 21
#define CFG_RING4_DESC_EN_MASK 0x00200000
#define CFG_RING4_PAYLOAD_EN_OFFSET 20
#define CFG_RING4_PAYLOAD_EN_MASK 0x00100000
#define CFG_RING4_DESC_OFFSET_OFFSET 10
#define CFG_RING4_DESC_OFFSET_MASK 0x000FFC00
#define CFG_RING4_PAYLOAD_OFFSET_OFFSET 0
#define CFG_RING4_PAYLOAD_OFFSET_MASK 0x000003FF

//-----------------------------------
#define CFG_RX_RING0_DBG_CNT_ADDR 0x00c0
#define RING0_RX_DBG_CNT_OFFSET 0
#define RING0_RX_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_RING1_DBG_CNT_ADDR 0x00c4
#define RING1_RX_DBG_CNT_OFFSET 0
#define RING1_RX_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_RING2_DBG_CNT_ADDR 0x00c8
#define RING2_RX_DBG_CNT_OFFSET 0
#define RING2_RX_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_RING3_DBG_CNT_ADDR 0x00cc
#define RING3_RX_DBG_CNT_OFFSET 0
#define RING3_RX_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_RING4_DBG_CNT_ADDR 0x00d0
#define RING4_RX_DBG_CNT_OFFSET 0
#define RING4_RX_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DBG_CNT_CLR_ADDR 0x00d4
#define CFG_RING4_RX_DBG_CLR_OFFSET 4
#define CFG_RING4_RX_DBG_CLR_MASK 0x00000010
#define CFG_RING3_RX_DBG_CLR_OFFSET 3
#define CFG_RING3_RX_DBG_CLR_MASK 0x00000008
#define CFG_RING2_RX_DBG_CLR_OFFSET 2
#define CFG_RING2_RX_DBG_CLR_MASK 0x00000004
#define CFG_RING1_RX_DBG_CLR_OFFSET 1
#define CFG_RING1_RX_DBG_CLR_MASK 0x00000002
#define CFG_RING0_RX_DBG_CLR_OFFSET 0
#define CFG_RING0_RX_DBG_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_RX_FC_DBG_CNT_ADDR 0x00d8
#define RX_FC_DBG_CNT_OFFSET 0
#define RX_FC_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_DBG_CNT_CLR_ADDR 0x00dc
#define CFG_RX_ABORT_DBG_CNT_CLR_OFFSET 2
#define CFG_RX_ABORT_DBG_CNT_CLR_MASK 0x00000004
#define CFG_PKT_DETECTED_DBG_CNT_CLR_OFFSET 1
#define CFG_PKT_DETECTED_DBG_CNT_CLR_MASK 0x00000002
#define CFG_RX_FC_DBG_CNT_CLR_OFFSET 0
#define CFG_RX_FC_DBG_CNT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_RX_PKT_DETECTED_CNT_ADDR 0x00e0
#define PKT_DETECTED_DBG_CNT_OFFSET 0
#define PKT_DETECTED_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TIMEOUT_0_ADDR 0x00e4
#define CFG_RX_VEC_TIMEOUT_OFFSET 16
#define CFG_RX_VEC_TIMEOUT_MASK 0xFFFF0000
#define CFG_RX_FC_TIMEOUT_OFFSET 0
#define CFG_RX_FC_TIMEOUT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_RX_TIMEOUT_1_ADDR 0x00e8
#define CFG_RX_PB_TIMEOUT_OFFSET 0
#define CFG_RX_PB_TIMEOUT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TIMEOUT_2_ADDR 0x00ec
#define CFG_RX_RESP_TX_TIMEOUT_OFFSET 0
#define CFG_RX_RESP_TX_TIMEOUT_MASK 0x000FFFFF

//-----------------------------------
#define CFG_RX_TIMEOUT_ACT_ADDR 0x00f0
#define CFG_TDMA_RX_ABORT_WAIT_CIFS_OFFSET 2
#define CFG_TDMA_RX_ABORT_WAIT_CIFS_MASK 0x00000004
#define CFG_MAC_RX_ABORT_ACT_OFFSET 1
#define CFG_MAC_RX_ABORT_ACT_MASK 0x00000002
#define CFG_RX_TIMEOUT_ACT_OFFSET 0
#define CFG_RX_TIMEOUT_ACT_MASK 0x00000001

//-----------------------------------
#define CFG_RX_ABORT_DBG_CNT_ADDR 0x00f4
#define RX_ABORT_DBG_CNT_OFFSET 0
#define RX_ABORT_DBG_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_DUMMY2_ADDR 0x00f8

//-----------------------------------
#define CFG_RX_DUMMY3_ADDR 0x00fc

//-----------------------------------
#define CFG_RX_DUMMY4_ADDR 0x0100

//-----------------------------------
#define CFG_RO_RX_NTB_TIMESTAMP_ADDR 0x0104
#define RX_NTB_TIMESTAMP_OFFSET 0
#define RX_NTB_TIMESTAMP_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RO_RX_LOCAL_TIMESTAMP_ADDR 0x0108
#define RX_LOCAL_TIMESTAMP_OFFSET 0
#define RX_LOCAL_TIMESTAMP_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RO_RX_ZC_OFFSET_ADDR 0x010C
#define RX_ZC_OFFSET_OFFSET 0
#define RX_ZC_OFFSET_MASK 0x0000FFFF

//-----------------------------------
#define CFG_RX_ABORT_DBG_CNT1_ADDR 0x0110
#define RX_FRAG_ABORT_DBG_CNT_OFFSET 16
#define RX_FRAG_ABORT_DBG_CNT_MASK 0xFFFF0000
#define TDMA_ABORT_RX_DBG_CNT_OFFSET 0
#define TDMA_ABORT_RX_DBG_CNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_RX_ABORT_DBG_CNT2_ADDR 0x0114
#define RX_TIMEOUT_ABORT_DBG_CNT_OFFSET 0
#define RX_TIMEOUT_ABORT_DBG_CNT_MASK 0x0000FFF

//HW module read/write macro
#define RGF_RX_READ_REG(addr) SOC_READ_REG(RGF_RX_BASEADDR + addr)
#define RGF_RX_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_RX_BASEADDR + addr,value)