kunlun/inc/hw/reg/riscv/13/intc_reg.h

//-----------------------------------
#define CFG_INTC_RVER_ADDR 0x0000
#define INTC_RF_VER_OFFSET 0
#define INTC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_INT_ENA0_ADDR 0x0004
#define INT_ENA0_OFFSET 0
#define INT_ENA0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_ENA1_ADDR 0x0008
#define INT_ENA1_OFFSET 0
#define INT_ENA1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_SRC0_ADDR 0x000c
#define INT_SRC0_OFFSET 0
#define INT_SRC0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_SRC1_ADDR 0x0010
#define INT_SRC1_OFFSET 0
#define INT_SRC1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_STS0_ADDR 0x0014
#define INT_STS0_OFFSET 0
#define INT_STS0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_STS1_ADDR 0x0018
#define INT_STS1_OFFSET 0
#define INT_STS1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_PRI_STS_ADDR 0x001c
#define INT_ID_OFFSET 8
#define INT_ID_MASK 0x00003F00
#define INT_PRI_STS_OFFSET 0
#define INT_PRI_STS_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_SEL_ADDR 0x0020
#define INT_PRI_SEL_OFFSET 0
#define INT_PRI_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG0_ADDR 0x0030
#define INT7_PRI_CFG_OFFSET 28
#define INT7_PRI_CFG_MASK 0x70000000
#define INT6_PRI_CFG_OFFSET 24
#define INT6_PRI_CFG_MASK 0x07000000
#define INT5_PRI_CFG_OFFSET 20
#define INT5_PRI_CFG_MASK 0x00700000
#define INT4_PRI_CFG_OFFSET 16
#define INT4_PRI_CFG_MASK 0x00070000
#define INT3_PRI_CFG_OFFSET 12
#define INT3_PRI_CFG_MASK 0x00007000
#define INT2_PRI_CFG_OFFSET 8
#define INT2_PRI_CFG_MASK 0x00000700
#define INT1_PRI_CFG_OFFSET 4
#define INT1_PRI_CFG_MASK 0x00000070
#define INT0_PRI_CFG_OFFSET 0
#define INT0_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG1_ADDR 0x0034
#define INT15_PRI_CFG_OFFSET 28
#define INT15_PRI_CFG_MASK 0x70000000
#define INT14_PRI_CFG_OFFSET 24
#define INT14_PRI_CFG_MASK 0x07000000
#define INT13_PRI_CFG_OFFSET 20
#define INT13_PRI_CFG_MASK 0x00700000
#define INT12_PRI_CFG_OFFSET 16
#define INT12_PRI_CFG_MASK 0x00070000
#define INT11_PRI_CFG_OFFSET 12
#define INT11_PRI_CFG_MASK 0x00007000
#define INT10_PRI_CFG_OFFSET 8
#define INT10_PRI_CFG_MASK 0x00000700
#define INT9_PRI_CFG_OFFSET 4
#define INT9_PRI_CFG_MASK 0x00000070
#define INT8_PRI_CFG_OFFSET 0
#define INT8_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG2_ADDR 0x0038
#define INT23_PRI_CFG_OFFSET 28
#define INT23_PRI_CFG_MASK 0x70000000
#define INT22_PRI_CFG_OFFSET 24
#define INT22_PRI_CFG_MASK 0x07000000
#define INT21_PRI_CFG_OFFSET 20
#define INT21_PRI_CFG_MASK 0x00700000
#define INT20_PRI_CFG_OFFSET 16
#define INT20_PRI_CFG_MASK 0x00070000
#define INT19_PRI_CFG_OFFSET 12
#define INT19_PRI_CFG_MASK 0x00007000
#define INT18_PRI_CFG_OFFSET 8
#define INT18_PRI_CFG_MASK 0x00000700
#define INT17_PRI_CFG_OFFSET 4
#define INT17_PRI_CFG_MASK 0x00000070
#define INT16_PRI_CFG_OFFSET 0
#define INT16_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG3_ADDR 0x003c
#define INT31_PRI_CFG_OFFSET 28
#define INT31_PRI_CFG_MASK 0x70000000
#define INT30_PRI_CFG_OFFSET 24
#define INT30_PRI_CFG_MASK 0x07000000
#define INT29_PRI_CFG_OFFSET 20
#define INT29_PRI_CFG_MASK 0x00700000
#define INT28_PRI_CFG_OFFSET 16
#define INT28_PRI_CFG_MASK 0x00070000
#define INT27_PRI_CFG_OFFSET 12
#define INT27_PRI_CFG_MASK 0x00007000
#define INT26_PRI_CFG_OFFSET 8
#define INT26_PRI_CFG_MASK 0x00000700
#define INT25_PRI_CFG_OFFSET 4
#define INT25_PRI_CFG_MASK 0x00000070
#define INT24_PRI_CFG_OFFSET 0
#define INT24_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG4_ADDR 0x0040
#define INT39_PRI_CFG_OFFSET 28
#define INT39_PRI_CFG_MASK 0x70000000
#define INT38_PRI_CFG_OFFSET 24
#define INT38_PRI_CFG_MASK 0x07000000
#define INT37_PRI_CFG_OFFSET 20
#define INT37_PRI_CFG_MASK 0x00700000
#define INT36_PRI_CFG_OFFSET 16
#define INT36_PRI_CFG_MASK 0x00070000
#define INT35_PRI_CFG_OFFSET 12
#define INT35_PRI_CFG_MASK 0x00007000
#define INT34_PRI_CFG_OFFSET 8
#define INT34_PRI_CFG_MASK 0x00000700
#define INT33_PRI_CFG_OFFSET 4
#define INT33_PRI_CFG_MASK 0x00000070
#define INT32_PRI_CFG_OFFSET 0
#define INT32_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG5_ADDR 0x0044
#define INT47_PRI_CFG_OFFSET 28
#define INT47_PRI_CFG_MASK 0x70000000
#define INT46_PRI_CFG_OFFSET 24
#define INT46_PRI_CFG_MASK 0x07000000
#define INT45_PRI_CFG_OFFSET 20
#define INT45_PRI_CFG_MASK 0x00700000
#define INT44_PRI_CFG_OFFSET 16
#define INT44_PRI_CFG_MASK 0x00070000
#define INT43_PRI_CFG_OFFSET 12
#define INT43_PRI_CFG_MASK 0x00007000
#define INT42_PRI_CFG_OFFSET 8
#define INT42_PRI_CFG_MASK 0x00000700
#define INT41_PRI_CFG_OFFSET 4
#define INT41_PRI_CFG_MASK 0x00000070
#define INT40_PRI_CFG_OFFSET 0
#define INT40_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG6_ADDR 0x0048
#define INT55_PRI_CFG_OFFSET 28
#define INT55_PRI_CFG_MASK 0x70000000
#define INT54_PRI_CFG_OFFSET 24
#define INT54_PRI_CFG_MASK 0x07000000
#define INT53_PRI_CFG_OFFSET 20
#define INT53_PRI_CFG_MASK 0x00700000
#define INT52_PRI_CFG_OFFSET 16
#define INT52_PRI_CFG_MASK 0x00070000
#define INT51_PRI_CFG_OFFSET 12
#define INT51_PRI_CFG_MASK 0x00007000
#define INT50_PRI_CFG_OFFSET 8
#define INT50_PRI_CFG_MASK 0x00000700
#define INT49_PRI_CFG_OFFSET 4
#define INT49_PRI_CFG_MASK 0x00000070
#define INT48_PRI_CFG_OFFSET 0
#define INT48_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG7_ADDR 0x004c
#define INT63_PRI_CFG_OFFSET 28
#define INT63_PRI_CFG_MASK 0x70000000
#define INT62_PRI_CFG_OFFSET 24
#define INT62_PRI_CFG_MASK 0x07000000
#define INT61_PRI_CFG_OFFSET 20
#define INT61_PRI_CFG_MASK 0x00700000
#define INT60_PRI_CFG_OFFSET 16
#define INT60_PRI_CFG_MASK 0x00070000
#define INT59_PRI_CFG_OFFSET 12
#define INT59_PRI_CFG_MASK 0x00007000
#define INT58_PRI_CFG_OFFSET 8
#define INT58_PRI_CFG_MASK 0x00000700
#define INT57_PRI_CFG_OFFSET 4
#define INT57_PRI_CFG_MASK 0x00000070
#define INT56_PRI_CFG_OFFSET 0
#define INT56_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INTER_MSIP_ADDR 0x0050
#define MSIP_REG_OFFSET 0
#define MSIP_REG_MASK 0x00000001

//-----------------------------------
#define CFG_INTER_MTIP_CTL1_ADDR 0x0054
#define MTIP_INT_FORCE_OFFSET 24
#define MTIP_INT_FORCE_MASK 0x01000000
#define MTIP_INT_EN_OFFSET 16
#define MTIP_INT_EN_MASK 0x00010000
#define MTIP_CNT_DONE_OFFSET 8
#define MTIP_CNT_DONE_MASK 0x00000100
#define MTIP_CNT_EN_OFFSET 0
#define MTIP_CNT_EN_MASK 0x00000001

//-----------------------------------
#define CFG_INTER_MTIP_CTL2_ADDR 0x0058
#define MTIP_CNT_INT_CLR_OFFSET 0
#define MTIP_CNT_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_INTER_MTIP_CNT_ADDR 0x005C
#define MTIP_CNT_OFFSET 0
#define MTIP_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INTER_MTIP_CMP_ADDR 0x0060
#define MTIP_CMP_OFFSET 0
#define MTIP_CMP_MASK 0xFFFFFFFF

//HW module read/write macro
#define INTC_READ_REG(addr) SOC_READ_REG(INTC_BASEADDR + addr)
#define INTC_WRITE_REG(addr,value) SOC_WRITE_REG(INTC_BASEADDR + addr,value)
#define INTC1_READ_REG(addr) SOC_READ_REG(INTC1_BASEADDR + addr)
#define INTC1_WRITE_REG(addr,value) SOC_WRITE_REG(INTC1_BASEADDR + addr,value)