66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
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//-----------------------------------
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#define CFG_EFUSE_INFO_ADDR 0x0000
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#define APB_RF_VER_OFFSET 0
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#define APB_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_EFUSE_CMD_ADDR 0x0004
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#define REG_IDLE_OFFSET 24
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#define REG_IDLE_MASK 0x01000000
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#define REG_PGM_OFFSET 16
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#define REG_PGM_MASK 0x00FF0000
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#define REG_A_OFFSET 0
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#define REG_A_MASK 0x000007FF
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//-----------------------------------
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#define CFG_EFUSE_ERR_CNT_ADDR 0x0008
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#define ERROR_BIT_CNT_OFFSET 0
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#define ERROR_BIT_CNT_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_EFUSE_REG_0_ADDR 0x0100
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#define EFUSE_0_OFFSET 0
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#define EFUSE_0_MASK 0xFFFFFFFF
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#if 0
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//-----------------------------------
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#define CFG_EFUSE_BITS32_1_ADDR 0x0104
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#define EFUSE_1_OFFSET 0
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#define EFUSE_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_2_ADDR 0x0108
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#define EFUSE_2_OFFSET 0
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#define EFUSE_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_3_ADDR 0x010C
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#define EFUSE_3_OFFSET 0
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#define EFUSE_3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_4_ADDR 0x0110
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#define EFUSE_4_OFFSET 0
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#define EFUSE_4_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_5_ADDR 0x0114
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#define EFUSE_5_OFFSET 0
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#define EFUSE_5_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_6_ADDR 0x0118
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#define EFUSE_6_OFFSET 0
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#define EFUSE_6_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_EFUSE_BITS32_7_ADDR 0x011C
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#define EFUSE_7_OFFSET 0
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#define EFUSE_7_MASK 0xFFFFFFFF
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#endif
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//HW module read/write macro
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#define EFUSE_DIG_READ_REG(addr) SOC_READ_REG(EFUSE_DIG_BASEADDR + addr)
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#define EFUSE_DIG_WRITE_REG(addr,value) SOC_WRITE_REG(EFUSE_DIG_BASEADDR + addr,value)
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