426 lines
11 KiB
C
426 lines
11 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "plc_fr.h"
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#include "mac_reset.h"
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#include "mac_sys_reg.h"
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#include "ahb.h"
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#include "hw_desc.h"
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#include "hw_phy_init.h"
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#include "mac_raw_reg.h"
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#include "mac_init_api.h"
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/* HW WAR for cfg reg not take effect */
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#include "mac_txq_hw.h"
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#include "mac_status.h"
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#include "mac_sched_hw.h"
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#include "tx_mpdu_start.h"
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#include "os_utils_api.h"
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#include "phy_reg.h"
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#include "mac_pdev.h"
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#include "iot_system_api.h"
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#include "os_task.h"
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#include "phy_phase.h"
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void enable_mac(uint32_t enable) {
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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if (enable) {
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ahb_mac_enable();
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} else {
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ahb_mac_disable();
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}
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#else
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(void)enable;
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#endif
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return;
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}
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void warm_rst_mac_hold() {
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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ahb_mac_reset_hold();
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#endif
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return;
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}
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void warm_rst_mac_release() {
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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ahb_mac_reset_release();
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#endif
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return;
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}
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void mac_cfg_reg_reset()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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ahb_mac_reset();
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/* Sadc stop working after phy reset, but dma still working, dma will move
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* error data to buffer. So, we need reset sadc after phy reset quickly.
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* See details at bugID:733.
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* 1:select the sadc data; 0:select adc 16-downsampling data.
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*/
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phy_adc_mon_sel_set(true);
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#endif
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return;
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}
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void mac_reset(MAC_RST_REASON_ID rst_reason) {
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(void)rst_reason;
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enable_mac(true);
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warm_rst_mac_hold();
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warm_rst_mac_release();
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/* not reset all reg here, as the cfg reg reset
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* not only reset mac reg, put it at phy_reset()
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*/
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}
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void mac_warm_reset_war(uint32_t flag) {
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(void)flag;
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if (flag == CONT_RX_ABORT4) {
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#if ENA_WAR_244
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/* disable MAC RAW DATA MODE */
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RGF_RAW_WRITE_REG(CFG_RAW_DATA_MODE_ADDR, 0);
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/* clear pb size BB */
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phy_rawdata_mode_bb_set_ps_tr(0,0,0);
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#endif
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} else if (flag == PHY_TX_HANG){
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mac_new_phy_cfg_apply();
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/* clear mac status cnt */
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mac_status_cnt_clr();
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}
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}
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void mac_set_sw_idle_mode(uint32_t ena, uint32_t is_idle) {
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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tmp = RGF_MAC_READ_REG(CFG_PHASE_BAND_SEL_ADDR);
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REG_FIELD_SET(CFG_SW_IDLE_MODE_EN, tmp, ena);
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REG_FIELD_SET(CFG_SW_IDLE_MODE, tmp, is_idle);
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RGF_MAC_WRITE_REG(CFG_PHASE_BAND_SEL_ADDR, tmp);
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#else
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(void)ena;
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(void)is_idle;
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#endif
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}
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uint32_t mac_wait_phy_txrx_idle() {
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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/* return 0 for wait idle successful
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* 1 for wait failed if timeout
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*/
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/* TODO: support timeout */
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uint32_t tmp;
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uint32_t tx_active;
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uint32_t rx_active;
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do {
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tmp = RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR);
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rx_active = REG_FIELD_GET(PHY_RX_ENABLE, tmp);
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tx_active = REG_FIELD_GET(PHY_TX_ENABLE, tmp);
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} while (tx_active && rx_active);
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#else
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#endif
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return 0;
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}
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void mac_force_phy_tx_ready(uint32_t ena, uint32_t is_force_ready) {
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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/* make phy tx ready to 1 before mac disable hwq */
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uint32_t tmp;
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
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REG_FIELD_SET(CFG_PHY_TX_READY_FORCE_EN, tmp, ena);
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REG_FIELD_SET(CFG_PHY_TX_READY, tmp, is_force_ready);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_2_ADDR, tmp);
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#else
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(void)ena;
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(void)is_force_ready;
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#endif
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return;
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}
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uint32_t mac_dbg_bus_is_in_tx()
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{
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#define TX_FSM_IS_TX_MASK 0x38000
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uint32_t debug_tmp;
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mac_set_debug_reg(0x100);
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debug_tmp = mac_rx_get_debug_reg();
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/* if 0, then means idle */
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return debug_tmp & TX_FSM_IS_TX_MASK;
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}
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void mac_tx_wait_all_queue_idle(uint32_t iscco, uint32_t time_ms)
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{
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uint32_t start_ts = os_boot_time32();
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#if DEBUG_HWQ_SHCED_HANG
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uint32_t try_cnt = 0;
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#endif
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while (mac_dbg_bus_is_in_tx()) {
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if (os_boot_time32() - start_ts > time_ms) {
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#if DEBUG_HWQ_SHCED_HANG
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try_cnt++;
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/* war for stop sched hang */
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if (try_cnt < 2) {
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/* force mac phy interface */
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mac_force_mac_phy_interface(1);
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os_delay(1);
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mac_force_mac_phy_interface(0);
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} else
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#endif
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{
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#if WAR_HWQ_SHCED_HANG
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/* reset chip */
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iot_system_restart(IOT_SYS_RST_REASON_MAC_TX_HANG);
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#endif
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/* if try_cnt >= 2 then assert */
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mac_dump_buf(MAC_DUMP_TYPE_4,
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(uint32_t *)mac_txq_get_curr_desc_ptr(\
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!!iscco, \
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false), \
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sizeof(tx_mpdu_start)/sizeof(uint32_t), \
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(uint32_t *)RGF_HWQ_BASEADDR, 108, \
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(uint32_t *)(PHY_BASEADDR + CFG_BB_RX_TD_DBG_BUS0_ADDR),
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38, true);
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}
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}
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}
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return;
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}
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void mac_sw_trig_need_en(bool_t ena)
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{
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/* for kunlun 1 we don't have this define */
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(void)ena;
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return;
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}
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void mac_sw_trig_start(bool_t ena)
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{
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/* for kunlun 1 we don't have this define */
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(void)ena;
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return;
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}
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void mac_dma_ckl_sel(bool_t ena)
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{
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/* for kunlun 1 we don't have this define */
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(void)ena;
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return;
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}
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uint32_t mac_get_phy_txrx_sts()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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uint32_t tx_active;
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uint32_t rx_active;
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tmp = RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR);
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rx_active = REG_FIELD_GET(PHY_RX_ENABLE, tmp);
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tx_active = REG_FIELD_GET(PHY_TX_ENABLE, tmp);
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if (rx_active == 0 && tx_active == 0) {
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return MAC_PHY_IDLE_STS;
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}
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else if (rx_active == 1 && tx_active == 0) {
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return MAC_PHY_RX_STS;
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}
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else if (rx_active == 0 && tx_active == 1) {
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return MAC_PHY_TX_STS;
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}
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else if (rx_active == 1 && tx_active == 1) {
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IOT_ASSERT(0);
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return MAC_PHY_UNKNOW_STS;
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}
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#else
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#endif
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return 0;
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}
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/* NOTE: this function cannot call in interrupt */
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uint32_t mac_set_sts_idle()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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phy_force_0_access_require();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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REG_FIELD_SET(CFG_PHY_RX_FRAME_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_RX_FRAME, tmp, 0);
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REG_FIELD_SET(CFG_PHY_RX_VLD_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_RX_VLD, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_CRC_DONE_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_FC_CRC_DONE, tmp, 0);
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REG_FIELD_SET(CFG_PHY_PB_CRC_DONE_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_PB_CRC_DONE, tmp, 0);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
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phy_force_0_access_release();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
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REG_FIELD_SET(CFG_PHY_PB_RCV_DONE_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_PB_RCV_DONE, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_RCV_DONE_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_FC_RCV_DONE, tmp, 0);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_1_ADDR, tmp);
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
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REG_FIELD_SET(CFG_PHY_TX_READY_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_TX_READY, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_2_ADDR, tmp);
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#else
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#endif
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return 0;
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}
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/* NOTE: this function cannot call in interrupt */
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uint32_t mac_free_sts_idle()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp;
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phy_force_0_access_require();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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REG_FIELD_SET(CFG_PHY_RX_FRAME_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_RX_FRAME, tmp, 0);
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REG_FIELD_SET(CFG_PHY_RX_VLD_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_RX_VLD, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_CRC_DONE_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_CRC_DONE, tmp, 0);
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REG_FIELD_SET(CFG_PHY_PB_CRC_DONE_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_PB_CRC_DONE, tmp, 0);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
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phy_force_0_access_release();
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
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REG_FIELD_SET(CFG_PHY_PB_RCV_DONE_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_PB_RCV_DONE, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_RCV_DONE_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_FC_RCV_DONE, tmp, 0);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_1_ADDR, tmp);
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
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REG_FIELD_SET(CFG_PHY_TX_READY_FORCE_EN, tmp, 0);
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REG_FIELD_SET(CFG_PHY_TX_READY, tmp, 0);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_2_ADDR, tmp);
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#else
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#endif
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return 0;
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}
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uint32_t mac_dbg_bus_get_mac_sts(uint32_t value, uint32_t mask)
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{
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uint32_t debug_tmp;
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mac_set_debug_reg(value);
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debug_tmp = mac_rx_get_debug_reg();
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/* if 0, then means idle */
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return debug_tmp & mask;
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}
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/* NOTE: this function cannot call in interrupt */
|
||
|
|
uint32_t mac_set_pcs_busy(uint32_t enable, uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
uint32_t tmp;
|
||
|
|
phy_force_0_access_require();
|
||
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
|
||
|
|
REG_FIELD_SET(CFG_PHY_PCS_BUSY_FORCE_EN, tmp, enable);
|
||
|
|
REG_FIELD_SET(CFG_PHY_PCS_BUSY, tmp, value);
|
||
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
|
||
|
|
phy_force_0_access_release();
|
||
|
|
#else
|
||
|
|
(void)enable;
|
||
|
|
(void)value;
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* NOTE: this function cannot call in interrupt */
|
||
|
|
uint32_t mac_set_fc_crc_done(uint32_t enable, uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
uint32_t tmp;
|
||
|
|
phy_force_0_access_require();
|
||
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
|
||
|
|
REG_FIELD_SET(CFG_PHY_FC_CRC_DONE_FORCE_EN, tmp, enable);
|
||
|
|
REG_FIELD_SET(CFG_PHY_FC_CRC_DONE, tmp, value);
|
||
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
|
||
|
|
phy_force_0_access_release();
|
||
|
|
#else
|
||
|
|
(void)enable;
|
||
|
|
(void)value;
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t mac_set_reg_tx_abort_debug_value()
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
uint32_t tmp;
|
||
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_ABORT_FORCE_EN, tmp, 1);
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_ABORT, tmp, 0);
|
||
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_1_ADDR, tmp);
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t mac_force_mac_phy_interface(uint32_t value)
|
||
|
|
{
|
||
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
||
|
|
uint32_t tmp;
|
||
|
|
tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
|
||
|
|
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_READY_FORCE_EN, tmp, value);
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_READY, tmp, value);
|
||
|
|
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_PROCESSING_FORCE_EN, tmp, value);
|
||
|
|
REG_FIELD_SET(CFG_PHY_TX_PROCESSING, tmp, value);
|
||
|
|
|
||
|
|
RGF_MAC_WRITE_REG(CFG_PHY_FORCE_2_ADDR, tmp);
|
||
|
|
#else
|
||
|
|
(void)value;
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|