kunlun/plc/halphy/hw2/phy_nf.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

/* os shim includes */
#include "iot_config.h"
#include "os_types.h"
#include "hw_reg_api.h"
#include "iot_errno_api.h"

/* driver includes */
#include "phy_nf.h"
#include "phy_bb.h"
#include "os_timer_api.h"
#include "phy_rxtd_reg.h"
#include "mac_sys_reg.h"
#include "iot_io.h"
#include "hw_phy_api.h"
#include "iot_system.h"
#include "phy_ana_reg.h"

/* callback for phy call mac dsr function */
phy_call_mac_dsr_cb_t phy_call_mac_dsr_cb = NULL;

/* callback for phy call mac spur function */
phy_call_mac_spur_cb_t phy_call_mac_spur_cb = NULL;

/* callback for phy call mac scan band function */
phy_call_mac_scan_band_cb_t phy_call_mac_scan_band_cb = NULL;

void register_phy_call_mac_dsr_cb(phy_call_mac_dsr_cb_t cb)
{
    phy_call_mac_dsr_cb = cb;
}

void register_phy_call_mac_spur_cb(phy_call_mac_spur_cb_t cb)
{
    phy_call_mac_spur_cb = cb;
}

void register_phy_call_mac_scan_band_cb(phy_call_mac_scan_band_cb_t cb)
{
    phy_call_mac_scan_band_cb = cb;
}

uint8_t phy_agc_acc_dly_get(void)
{
    uint32_t tmp = 0;
    uint8_t dly_exp = 0;

    /*
    * get 20ms dly for different acc step
    *  192/ 384/ 768/ 1536/ 3072/ 6144/
    */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
    switch(REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp))
    {
        case 0: dly_exp = 13; break;
        case 1: dly_exp = 12; break;
        case 2: dly_exp = 11; break;
        case 3: dly_exp = 10; break;
        case 4: dly_exp = 9;  break;
        case 5: dly_exp = 8;  break;
        default: dly_exp = 10; break;
    }

    return dly_exp;
}

void phy_cal_nf_systick_stop()
{
}

void phy_cal_nf_on_3phase()
{
}

void phy_snr_cal_timer_handler()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;
    uint8_t dly_exp = 0;
    uint8_t current_nf = 0;
    static uint8_t cnt = 0;
    iot_phy_sts_info_t total_sts = {0};

    /* check cal noise done  */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
    if(REG_FIELD_GET(SW_CAL_NOISE_DONE,tmp))
    {
        current_nf = REG_FIELD_GET(SW_CAL_NOISE_PWR,tmp);
        /*121 is reset value, not valid value*/
        if (current_nf != PHY_NF_RST_VAL) {
            g_phy_ctxt.dep.nf = current_nf;
        }
    }

    /* update cpu share nf */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
    switch(REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp))
    {
        case 0:
            g_phy_cpu_share_ctxt.nf_192p = g_phy_ctxt.dep.nf;
            break;
        case 1:
            g_phy_cpu_share_ctxt.nf_384p = g_phy_ctxt.dep.nf;
            break;
        case 2:
            g_phy_cpu_share_ctxt.nf_768p = g_phy_ctxt.dep.nf;
            break;
        case 3:
            g_phy_cpu_share_ctxt.nf_1536p = g_phy_ctxt.dep.nf;
            break;
        case 4:
            g_phy_cpu_share_ctxt.nf_3072p = g_phy_ctxt.dep.nf;
            break;
        case 5:
            g_phy_cpu_share_ctxt.nf_6144p = g_phy_ctxt.dep.nf;
            break;
        default:
            break;
    }

    /* get dly depend on ACC_STEP */
    dly_exp = phy_agc_acc_dly_get();

    /* config dly */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
    REG_FIELD_SET(SW_CAL_NOISE_DLY_EXP, tmp, dly_exp);
    PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);

    /* trig again */
    tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
    REG_FIELD_SET(SW_CAL_NOISE_START, tmp, 1);
    PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);

    /* print current noise floor */
    iot_printf("[PHY] nf:%d, rx_phase:%d\n", \
        g_phy_ctxt.dep.nf, \
        (RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR) & \
            PHY_RX_PHASE_SEL_MASK) >> PHY_RX_PHASE_SEL_OFFSET);

    if (phy_get_fw_mode() == MM_MODE && \
        cnt >= 3) {
        phy_sts_get(&total_sts);
        iot_printf("mac tx ok:%d/4s, fc_ok:%d/4s, fc_err:%d/4s,", \
            total_sts.mac_tx_ok_cnt, total_sts.fc_crc_ok_cnt, \
            total_sts.fc_crc_fail_cnt);
        iot_printf("pld_ok:%d/4s, pld fail:%d/4s, sync ok:%d/4s, tempt:%d\r\n", \
            total_sts.pld_crc_ok_cnt, total_sts.pld_crc_fail_cnt, \
            total_sts.sync_ok_cnt, total_sts.phy_tempt_celsius);

        iot_printf("ANA_TOP:%x ",PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR));

        iot_printf("F_0:%x F_1:%x F_2:%x ",\
            RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR), \
            RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR), \
            RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR));

        extern uint32_t mac_get_tx_rifs();
        iot_printf("INTF_0:%x INTF_1:%x, rifs:%lu\r\n", \
            RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR),\
            RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_1_ADDR),
            mac_get_tx_rifs());

        /* update log cnt */
        g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_ok_cnt += \
            total_sts.fc_crc_ok_cnt;
        g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt += \
            total_sts.fc_crc_fail_cnt;
        g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_ok_cnt += \
            total_sts.pld_crc_ok_cnt;
        g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_fail_cnt += \
            total_sts.pld_crc_fail_cnt;
        g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pkt_cnt += \
            total_sts.sync_ok_cnt;
        g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt += total_sts.mac_tx_ok_cnt;

        cnt = 0;
    } else {
        cnt++;
    }

    /* overstress handle */
    phy_overstress_timer_handler();

    if (phy_call_mac_scan_band_cb) {
        phy_call_mac_scan_band_cb();
    }

    if (phy_call_mac_spur_cb) {
        phy_call_mac_spur_cb();
    }

#endif
}

void phy_timer_handle()
{
    if (phy_call_mac_dsr_cb) {
       phy_call_mac_dsr_cb();
    }
}

uint32_t phy_nf_timer_start()
{
    uint32_t ret = ERR_FAIL;

#if HW_PLATFORM >= HW_PLATFORM_FPGA
    if (g_phy_ctxt.dep.phy_snr_cal_timer == 0) {
#if IOT_DTEST_ONLY_SUPPORT == 0
        g_phy_ctxt.dep.phy_snr_cal_timer = \
            os_create_timer(PLC_PHY_COMMON_MID, true,
            phy_timer_handle, NULL);
#else
        g_phy_ctxt.dep.phy_snr_cal_timer = \
            os_create_timer(PLC_PHY_COMMON_MID, true,
            phy_snr_cal_timer_handler, NULL);
#endif
        os_start_timer(g_phy_ctxt.dep.phy_snr_cal_timer, \
            PHY_SNR_CAL_TIMER_PERIOD);
    }
#endif

    return ret;
}