142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef _ROM_H_
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#define _ROM_H_
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#include <stdint.h>
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typedef unsigned int UINT32;
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typedef unsigned short UINT16;
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#ifndef NULL
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#define NULL 0
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#endif
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#define REG32(a) (*((volatile UINT32 *)(a)))
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#ifndef BIT
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#define BIT(b) (1<<(b))
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#endif
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#define DEFAULT_PLL_FRQ 25000000
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#define ROM_HASH_IV_LEN 16
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#define ROM_AES_KEY_LEN 16
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typedef struct vendor_config
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{
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uint16_t checksum;
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uint8_t program_done;
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uint8_t test_en;
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uint8_t bond_valid;
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uint8_t sfc_cfg_valid;
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uint8_t mac[6];
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uint8_t gpio_sfc_clk;
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uint8_t gpio_sfc_cs;
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uint8_t gpio_sfc_d0;
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uint8_t gpio_sfc_d1;
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uint8_t gpio_sfc_d2;
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uint8_t gpio_sfc_d3;
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uint8_t flash_cmd_valid;
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uint8_t flash_cmd_read;
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uint8_t flash_cmd_enable;
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uint8_t flash_cmd_reset;
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uint8_t chip_id;
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}vendor_config;
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typedef struct user_config
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{
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uint16_t checksum;
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uint8_t program_done;
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uint8_t cfg_valid;
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uint8_t uart_jtag0_enable;
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uint8_t uart_jtag1_enable;
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uint8_t jtag0_enable;
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uint8_t jtag1_enable;
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uint8_t cpu0_efuse_rd_enable;
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uint8_t cpu1_flash_key_rd_enable;
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uint8_t security_mode;
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uint8_t boot_mode;
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uint8_t flash_mode;
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uint8_t download_enable;
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}user_config;
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typedef struct user_key
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{
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uint8_t hash_iv[ROM_HASH_IV_LEN];
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uint8_t aes_key[ROM_AES_KEY_LEN];
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}user_key;
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typedef struct efuse_config
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{
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vendor_config v_config;
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user_config u_config;
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user_key u_key;
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}efuse_config;
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/* --------------------- APB --------------------------- */
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typedef enum {
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APB_UART0 = BIT(0),
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APB_GPIO = BIT(1),
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APB_GPTMR = BIT(2),
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APB_GMTX = BIT(2),
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APB_PIN = BIT(6),
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APB_WDG0 = BIT(13),
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APB_UART_MEM = BIT(16),
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}APB_MODULE;
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typedef enum {
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SEC_EMC = BIT(0),
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SEC_EFUSE = BIT(2),
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}SEC_GLB_MODULE;
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typedef enum {
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AHB_ICACHE = BIT(3),
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AHB_DCACHE = BIT(4),
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}AHB_GLB_MODULE;
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/* For serial flash controller (SFC) */
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#define SFC_BUFFER_SIZE 256
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#define SFC_BUFFER_ADDR 0x61000000
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#define REG_SFC_BASE 0x61000100
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#define REG_SFC_CMD0 (0x04 + REG_SFC_BASE)
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#define REG_SFC_CMD1 (0x08 + REG_SFC_BASE)
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#define REG_SFC_CFG1 (0x40 + REG_SFC_BASE)
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#define REG_SFC_RDATA (0x4C + REG_SFC_BASE)
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#define REG_SFC_WDATA (0x50 + REG_SFC_BASE)
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#define REG_SFC_DBG (0x54 + REG_SFC_BASE)
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#define REG_SFC_SWM_CFG0 (0x80 + REG_SFC_BASE)
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#define REG_SFC_SWM_CFG1 (0x84 + REG_SFC_BASE)
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#define REG_SFC_SWM_CFG2 (0x88 + REG_SFC_BASE)
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#define REG_SFC_CACHE_CFG0 (0x8C + REG_SFC_BASE)
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#define REG_SFC_CACHE_CFG1 (0x90 + REG_SFC_BASE)
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#define REG_SFC_WIM_CFG0 (0x94 + REG_SFC_BASE)
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#define REG_SFC_WIM_CFG1 (0x98 + REG_SFC_BASE)
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#define REG_SFC_RSM_CFG0 (0x9C + REG_SFC_BASE)
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#define REG_SFC_RSM_CFG1 (0xA0 + REG_SFC_BASE)
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#define REG_SFC_SUS_CFG0 (0xA4 + REG_SFC_BASE)
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#define REG_SFC_SUS_CFG1 (0xA8 + REG_SFC_BASE)
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typedef struct
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{
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UINT16 dTpye;
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UINT16 iTpye;
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UINT32 sOff;
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UINT32 iLen;
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}flTb;
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#endif
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