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kunlun/plc/halphy/hw2/phy_status.c

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2024-09-28 14:24:04 +08:00
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "phy_status.h"
#include "phy_bb.h"
#include "hw_tonemask.h"
#include "hw_reg_api.h"
#include "phy_dfe_reg.h"
#include "phy_tx_reg.h"
#include "phy_reg.h"
#include "phy_ana.h"
#include "phy_txrx_pwr.h"
#include "hw_phy_api.h"
#include "iot_dbglog_api.h"
#include "iot_dbglog.h"
#include "iot_io.h"
#if DEG_TX_ABORT
#include "mac_tmr_reg.h"
#include "mac_raw_reg.h"
#include "mac_sys_reg.h"
#endif
/* 30 minutes period, uint 10 mimutes */
#define PHY_PERIOD_30_MIN 3
/* 60 minutes period, uint 10 mimutes */
#define PHY_PERIOD_60_MIN 6
static uint8_t g_phy_period_30_min_cnt = 0, g_phy_period_60_min_cnt = 0;
uint32_t phy_get_rx_dc()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
volatile uint16_t dc_pgf = 0;
volatile uint16_t dc_pga = 0;
/* scan each gain */
uint8_t i;
for(i = 0; i < 8; i++)
{
phy_pgf_pga_dc_cal_get(i+77, &dc_pgf, &dc_pga);
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[i] = dc_pga;
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[i] = dc_pga;
}
#endif
return 0;
}
/* dc comp */
void phy_dc_comp_gain_get(volatile uint16_t *gain0, volatile uint16_t *gain1,
volatile uint16_t *gain2, volatile uint16_t *gain3)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = 0;
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP0_ADDR);
*gain0 = (uint16_t)REG_FIELD_GET(SW_DC_COMP_GAIN0, tmp);
*gain1 = (uint16_t)REG_FIELD_GET(SW_DC_COMP_GAIN1, tmp);
tmp = PHY_DFE_READ_REG(CFG_BB_DC_COMP1_ADDR);
*gain2 = (uint16_t)REG_FIELD_GET(SW_DC_COMP_GAIN2, tmp);
*gain3 = (uint16_t)REG_FIELD_GET(SW_DC_COMP_GAIN3, tmp);
#else
(void)gain0;
(void)gain1;
(void)gain2;
(void)gain3;
#endif
}
uint32_t phy_get_tx_dc()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
volatile uint16_t tx_dc_gain0 = 0;
volatile uint16_t tx_dc_gain1 = 0;
volatile uint16_t tx_dc_gain2 = 0;
volatile uint16_t tx_dc_gain3 = 0;
phy_dc_comp_gain_get(&tx_dc_gain0, &tx_dc_gain1,\
&tx_dc_gain2, &tx_dc_gain3);
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[0] = tx_dc_gain0;
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[1] = tx_dc_gain1;
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[2] = tx_dc_gain2;
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[3] = tx_dc_gain3;
#endif
return 0;
}
uint32_t phy_add_dc_cal_cnt()
{
g_phy_ctxt.dep.phy_status.dc_cal_cnt++;
return 0;
}
uint32_t phy_get_dc_cal_cnt()
{
return g_phy_ctxt.dep.phy_status.dc_cal_cnt;
}
uint32_t IRAM_ATTR phy_add_overstress_cnt()
{
g_phy_ctxt.indep.ovs_ctxt.os_cnt++;
g_phy_ctxt.indep.ovs_ctxt.no_ovs_cnt = 0;
return 0;
}
uint32_t phy_get_overstress_cnt()
{
return g_phy_ctxt.indep.ovs_ctxt.os_cnt;
}
uint32_t phy_get_periodic_fc_err_num()
{
return g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt_clr;
}
uint32_t phy_get_rxtd_reg_tx_pkt()
{
iot_phy_sts_info_t pkt_sts;
phy_sts_get(&pkt_sts);
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_ok_cnt = \
pkt_sts.fc_crc_ok_cnt;
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt = \
pkt_sts.fc_crc_fail_cnt;
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_ok_cnt = \
pkt_sts.pld_crc_ok_cnt;
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_fail_cnt = \
pkt_sts.pld_crc_fail_cnt;
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pkt_cnt = \
pkt_sts.sync_ok_cnt;
g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt = pkt_sts.mac_tx_ok_cnt;
return 0;
}
#if 0
uint32_t phy_get_granite_reg()
{
uint32_t i;
uint8_t rodata = 0;
uint32_t rdata = 0;
for(i = 0; i < 11; i++)
{
phy_ana_i2c_read(i, &rdata, &rodata);
g_phy_ctxt.dep.phy_status.granite_reg[i] = rdata; //需要改
}
return 0;
}
#endif
uint32_t phy_get_txfd_reg()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd0 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR);
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd1 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR);
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd2 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR);
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd0 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR);
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd1 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR);
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd2 = \
PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR);
#endif
return 0;
}
uint32_t phy_get_dfe_reg()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
g_phy_ctxt.dep.phy_status.phy_gain_adjust_info = \
PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
#endif
return 0;
}
uint32_t phy_get_version()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
g_phy_ctxt.dep.phy_status.phy_mode = \
PHY_READ_REG(CFG_BB_VERSION_ADDR);
#endif
return 0;
}
uint32_t phy_get_band_cfg()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b0 = \
PHY_READ_REG(CFG_BB_R0_B0_TONE_ADDR);
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b1 = \
PHY_READ_REG(CFG_BB_R0_B1_TONE_ADDR);
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b2 = \
PHY_READ_REG(CFG_BB_R0_B2_TONE_ADDR);
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b0 = \
PHY_READ_REG(CFG_BB_R1_B0_TONE_ADDR);
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b1 = \
PHY_READ_REG(CFG_BB_R1_B1_TONE_ADDR);
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b2 = \
PHY_READ_REG(CFG_BB_R1_B2_TONE_ADDR);
#endif
return 0;
}
uint16_t phy_set_init_cnt()
{
g_phy_ctxt.dep.phy_status.phy_init_cnt++;
return 0;
}
uint16_t phy_get_init_cnt()
{
return g_phy_ctxt.dep.phy_status.phy_init_cnt;
}
uint16_t phy_set_reinit_cnt()
{
g_phy_ctxt.dep.phy_status.phy_reinit_cnt++;
return 0;
}
uint16_t phy_get_reinit_cnt()
{
return g_phy_ctxt.dep.phy_status.phy_reinit_cnt;
}
void phy_print_ana_dbg_info()
{
}
uint32_t phy_get_status()
{
phy_get_rx_dc();
phy_get_tx_dc();
phy_get_dc_cal_cnt();
phy_get_overstress_cnt();
/* update by log print, share with flash log */
//phy_get_rxtd_reg_tx_pkt();
//phy_get_granite_reg();
phy_get_txfd_reg();
phy_get_dfe_reg();
phy_get_version();
phy_get_band_cfg();
return 0;
}
void phy_get_status_printf()
{
phy_get_status();
if (++g_phy_period_60_min_cnt >= PHY_PERIOD_60_MIN) {
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS0_ID, 9,\
g_phy_ctxt.dep.phy_status.ppm_value,\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[0],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[0],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[1],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[1],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[2],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[2],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[3],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[3]);
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS1_ID, 9,\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[4],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[4],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[5],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[5],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[6],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[6],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pga[7],\
g_phy_ctxt.dep.phy_status.gain_dc.rx_dc_pgf[7],\
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[0]);
g_phy_period_60_min_cnt = 0;
}
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS2_ID, 9,\
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[1],\
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[2],\
g_phy_ctxt.dep.phy_status.gain_dc.tx_dc[3],\
g_phy_ctxt.dep.phy_status.dc_cal_cnt,\
g_phy_ctxt.indep.ovs_ctxt.os_cnt,\
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pkt_cnt,\
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_ok_cnt,\
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_fc_fail_cnt,\
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_ok_cnt);
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS3_ID, 9,\
g_phy_ctxt.dep.phy_status.phy_rx_cnt.phy_rx_pld_fail_cnt,\
g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt,\
g_phy_ctxt.dep.phy_status.granite_reg[0],\
g_phy_ctxt.dep.phy_status.granite_reg[1],\
g_phy_ctxt.dep.phy_status.granite_reg[2],\
g_phy_ctxt.dep.phy_status.granite_reg[3],\
g_phy_ctxt.dep.phy_status.granite_reg[4],\
g_phy_ctxt.dep.phy_status.granite_reg[5],\
g_phy_ctxt.dep.phy_status.granite_reg[6]);
if (++g_phy_period_30_min_cnt >= PHY_PERIOD_30_MIN) {
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS4_ID, 9,\
g_phy_ctxt.dep.phy_status.granite_reg[7],\
g_phy_ctxt.dep.phy_status.granite_reg[8],\
g_phy_ctxt.dep.phy_status.granite_reg[9],\
g_phy_ctxt.dep.phy_status.granite_reg[10],\
g_phy_ctxt.dep.phy_status.temp_res,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd0,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd1,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt0_bd2,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd0);
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS5_ID, 8,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd1,\
g_phy_ctxt.dep.phy_status.phy_tx_pwr_reg.bb_rt1_bd2,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b0,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b1,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r0_b2,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b0,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b1,\
g_phy_ctxt.dep.phy_status.phy_band.bb_r1_b2);
g_phy_period_30_min_cnt = 0;
}
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS6_ID, 5,\
g_phy_ctxt.dep.phy_status.phy_gain_adjust_info,\
g_phy_ctxt.dep.phy_status.phy_mode, \
g_phy_ctxt.dep.phy_status.spur_array[9],\
phy_get_init_cnt(),\
phy_get_reinit_cnt());
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS7_ID, 9,\
g_phy_ctxt.dep.phy_status.spur_array[0],\
g_phy_ctxt.dep.phy_status.spur_array[1],\
g_phy_ctxt.dep.phy_status.spur_array[2],\
g_phy_ctxt.dep.phy_status.spur_array[3],\
g_phy_ctxt.dep.phy_status.spur_array[4],\
g_phy_ctxt.dep.phy_status.spur_array[5],\
g_phy_ctxt.dep.phy_status.spur_array[6],\
g_phy_ctxt.dep.phy_status.spur_array[7],\
g_phy_ctxt.dep.phy_status.spur_array[8]);
iot_dbglog_input(PLC_PHY_STATUS_MID, DBGLOG_ERR,
IOT_PHY_STATUS8_ID, 7,\
g_phy_cpu_share_ctxt.nf_192p,\
g_phy_cpu_share_ctxt.nf_384p,\
g_phy_cpu_share_ctxt.nf_768p,\
g_phy_cpu_share_ctxt.nf_1536p,\
g_phy_cpu_share_ctxt.nf_3072p,\
g_phy_cpu_share_ctxt.nf_6144p,\
phy_spike_shift_en_get());
}
void phy_tx_dbg_cnt_clr(void)
{
uint32_t tmp = 0;
tmp = PHY_READ_REG(CFG_BB_TX_END_FRM_CNT_ADDR);
REG_FIELD_SET(PHY_TX_ABORT_CNT_CLR, tmp, 1);
REG_FIELD_SET(PHY_TX_DONE_CNT_CLR, tmp, 1);
PHY_WRITE_REG(CFG_BB_TX_END_FRM_CNT_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_TX_ST_FRM_CNT_ADDR);
REG_FIELD_SET(PHY_TX_PRS_CNT_CLR, tmp, 1);
REG_FIELD_SET(PHY_TX_START_CNT_CLR, tmp, 1);
PHY_WRITE_REG(CFG_BB_TX_ST_FRM_CNT_ADDR, tmp);
}
uint32_t phy_get_tx_abort_info()
{
#if DEG_TX_ABORT
uint32_t tmp;
uint32_t sw_is_tx_rawdata;
uint32_t sw_timeout_en;
uint32_t tx_abort_cnt;
tmp = PHY_READ_REG(CFG_BB_TX_END_FRM_CNT_ADDR);
tx_abort_cnt = REG_FIELD_GET(PHY_TX_ABORT_CNT, tmp);
if (g_phy_ctxt.dep.tx_abort_cnt != tx_abort_cnt) {
g_phy_ctxt.dep.tx_abort_cnt = tx_abort_cnt;
tmp = PHY_READ_REG(CFG_BB_RAW_DATA_MODE_CTRL_ADDR);
sw_is_tx_rawdata = REG_FIELD_GET(SW_IS_TX_RAW_DATA_MODE, tmp);
tmp = PHY_TX_READ_REG(CFG_BB_TX_WAROUND_CTRL_ADDR);
sw_timeout_en = REG_FIELD_GET(SW_TIME_OUT_EN, tmp);
iot_printf("HW dbg log, sw_is_tx_rawdata:0x%x, sw_timeout_en:0x%x,"\
"tx_abort_cnt = %d,"
"lock_vl:0x%x, phy_tx_int_raw:0x%x, mac_30:0x%x,"
"sts_0:0x%x, sts_1:0x%x,sts_2:0x%x,sts_3:0x%x,"\
"sts_4:0x%x, sts_5:0x%x,sts_6:0x%x,sts_7:0x%x,"\
"mtd0:0x%x, mtd1:0x%x, mtd2:0x%x, mtd3:0x%x, mtd4:0x%x,mtd5:0x%x\n"\
"timestap:0x%x, cur_ptr_lat:0x%x, tx_fc0:0x%x, tx_fc1:0x%x,"\
"tx_fc2:%x, tx_fc3:%x, pb_sumnum:0x%x\n",\
sw_is_tx_rawdata,\
sw_timeout_en,\
g_phy_ctxt.dep.tx_abort_cnt,\
g_phy_ctxt.dep.phy_dbg_bus_lock_value,\
g_phy_ctxt.dep.phy_tx_int_raw,\
g_phy_ctxt.dep.mac_reg_30,\
g_phy_ctxt.dep.dbg_sts_0,\
g_phy_ctxt.dep.dbg_sts_1,\
g_phy_ctxt.dep.dbg_sts_2,\
g_phy_ctxt.dep.dbg_sts_3,\
g_phy_ctxt.dep.dbg_sts_4,\
g_phy_ctxt.dep.dbg_sts_5,\
g_phy_ctxt.dep.dbg_sts_6,\
g_phy_ctxt.dep.dbg_sts_7,\
g_phy_ctxt.dep.mac_tx_data_0,\
g_phy_ctxt.dep.mac_tx_data_1,\
g_phy_ctxt.dep.mac_tx_data_2,\
g_phy_ctxt.dep.mac_tx_data_3,\
g_phy_ctxt.dep.mac_tx_data_4,\
g_phy_ctxt.dep.mac_tx_data_5,\
g_phy_ctxt.dep.timestap,\
g_phy_ctxt.dep.cur_ptr_lat,\
g_phy_ctxt.dep.tx_fc0,\
g_phy_ctxt.dep.tx_fc1,\
g_phy_ctxt.dep.tx_fc2,\
g_phy_ctxt.dep.tx_fc3,\
g_phy_ctxt.dep.pb_sumnum
);
}
#endif
return 0;
}
void phy_set_sw_time_out_en(uint8_t flag)
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
uint32_t tmp = PHY_TX_READ_REG(CFG_BB_TX_WAROUND_CTRL_ADDR);
REG_FIELD_SET(SW_TIME_OUT_EN, tmp, !!flag);
PHY_TX_WRITE_REG(CFG_BB_TX_WAROUND_CTRL_ADDR, tmp);
#else
(void)flag;
#endif
return;
}
void phy_dbg_set_tx_abort_reg()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
#if DEG_TX_ABORT
uint32_t tmp;
tmp = PHY_READ_REG(CFG_BB_DBG_BUS_SEL_ADDR);
REG_FIELD_SET(BB_DBG_BUS_SEL, tmp, 0);
PHY_WRITE_REG(CFG_BB_DBG_BUS_SEL_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR);
REG_FIELD_SET(SW_PHY_DBG_BUS_LOCK_CHOS, tmp, 43);
REG_FIELD_SET(SW_PHY_DBG_BUS_LOCK_ENA, tmp, 1);
PHY_WRITE_REG(CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR, tmp);
tmp = RGF_TMR_READ_REG(CFG_PHY_TX_TIMEOUT_ADDR);
REG_FIELD_SET(CFG_PHY_TX_TIMEOUT_EN, tmp, 0);
RGF_TMR_WRITE_REG(CFG_PHY_TX_TIMEOUT_ADDR, tmp);
tmp = PHY_READ_REG(CFG_BB_PHY_MPI_CTRL_ADDR);
REG_FIELD_SET(SW_MAC_BAND_RATE_SEL, tmp, 1);
PHY_WRITE_REG(CFG_BB_PHY_MPI_CTRL_ADDR, tmp);
g_phy_ctxt.dep.tx_abort_cnt= 0;
#endif
#else
(void);
#endif
return;
}
void IRAM_ATTR phy_dbg_get_tx_abort_lock_value()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
#if DEG_TX_ABORT
uint32_t tmp;
volatile uint8_t flag = 1;
uint32_t cur_time = 0;
int64_t time_span = 0;
uint32_t start_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
do {
cur_time = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
time_span = cur_time - start_time;
if (time_span < 0) { // wrap around
time_span = (0x100000000LL) - start_time + cur_time;
}
/* if timeout 10us , assert */
if (time_span > 25 * 10) {
IOT_ASSERT(0);
}
tmp = PHY_READ_REG(CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR);
/* wait lock enable = 0 */
if (!REG_FIELD_GET(SW_PHY_DBG_BUS_LOCK_ENA, tmp)) {
flag = 0;
/* record lock value */
g_phy_ctxt.dep.phy_dbg_bus_lock_value = \
PHY_READ_REG(CFG_BB_PHY_DBG_BUS_LOCK_VALUE_ADDR);
g_phy_ctxt.dep.phy_tx_int_raw = \
PHY_TX_READ_REG(CFG_BB_TX_INT_RAW_ADDR);
/* clr int */
PHY_TX_WRITE_REG(CFG_BB_TX_INT_CLR_ADDR, \
g_phy_ctxt.dep.phy_tx_int_raw);
g_phy_ctxt.dep.mac_reg_30 = \
RGF_MAC_READ_REG(CFG_TX_DBG_CTRL_ADDR);
g_phy_ctxt.dep.dbg_sts_0 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_0_ADDR);
g_phy_ctxt.dep.dbg_sts_1 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_1_ADDR);
g_phy_ctxt.dep.dbg_sts_2 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_2_ADDR);
g_phy_ctxt.dep.dbg_sts_3 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_3_ADDR);
g_phy_ctxt.dep.dbg_sts_4 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_4_ADDR);
g_phy_ctxt.dep.dbg_sts_5 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_5_ADDR);
g_phy_ctxt.dep.dbg_sts_6 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_6_ADDR);
g_phy_ctxt.dep.dbg_sts_7 =\
PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_STS_7_ADDR);
/*clear all sts registers*/
tmp = PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_CTRL_ADDR);
REG_FIELD_SET(SW_TX_ABORT_DBG_CLR, tmp, 1);
PHY_TX_WRITE_REG(CFG_BB_TX_ABORT_DBG_CTRL_ADDR, tmp);
/* release for HW next lock */
tmp = PHY_TX_READ_REG(CFG_BB_TX_ABORT_DBG_CTRL_ADDR);
REG_FIELD_SET(SW_TX_ABORT_DBG_LOCK_CLR, tmp, 1);
PHY_TX_WRITE_REG(CFG_BB_TX_ABORT_DBG_CTRL_ADDR, tmp);
/* set lock enable = 1 */
tmp = PHY_READ_REG(CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR);
REG_FIELD_SET(SW_PHY_DBG_BUS_LOCK_ENA, tmp, 1);
PHY_WRITE_REG(CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR, tmp);
g_phy_ctxt.dep.mac_tx_data_0 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA0_ADDR);
g_phy_ctxt.dep.mac_tx_data_1 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA1_ADDR);
g_phy_ctxt.dep.mac_tx_data_2 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA2_ADDR);
g_phy_ctxt.dep.mac_tx_data_3 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA3_ADDR);
g_phy_ctxt.dep.mac_tx_data_4 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA4_ADDR);
g_phy_ctxt.dep.mac_tx_data_5 = RGF_MAC_READ_REG(CFG_MAC_TX_DATA5_ADDR);
g_phy_ctxt.dep.timestap = RGF_RAW_READ_REG(CFG_TX_TIMESTAP_ADDR);
g_phy_ctxt.dep.cur_ptr_lat = RGF_RAW_READ_REG(CFG_TX_CUR_PTR_LAT_ADDR);
g_phy_ctxt.dep.tx_fc0 = RGF_RAW_READ_REG(CFG_DESC_SW_TX_FC0_ADDR);
g_phy_ctxt.dep.tx_fc1 = RGF_RAW_READ_REG(CFG_DESC_SW_TX_FC1_ADDR);
g_phy_ctxt.dep.tx_fc2 = RGF_RAW_READ_REG(CFG_DESC_SW_TX_FC2_ADDR);
g_phy_ctxt.dep.tx_fc3 = RGF_RAW_READ_REG(CFG_DESC_SW_TX_FC3_ADDR);
g_phy_ctxt.dep.pb_sumnum = RGF_RAW_READ_REG(CFG_DESC_PB_SYMNUM_ADDR);
}
} while(flag);
#endif
#else
(void);
#endif
return;
}
void phy_dump_busy_set(bool_t en)
{
(void)en;
}
bool_t phy_busy_get(void *phy_ctxt, PHY_BUSY_ID id)
{
(void)id;
(void)phy_ctxt;
return false;
}
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