kunlun/inc/hw/reg/riscv2/15/dvp_rf.h

//-----------------------------------
#define CFG_DCAM_CTRL_ADDR 0x00
#define BYPASS_EN_SHD_OFFSET 22
#define BYPASS_EN_SHD_MASK 0x00400000
#define FRAME_SKIP_CNT_OFFSET 18
#define FRAME_SKIP_CNT_MASK 0x003C0000
#define DCAM_FRAME_FORCE_EN_OFFSET 17
#define DCAM_FRAME_FORCE_EN_MASK 0x00020000
#define CONVERT_MODE_OFFSET 15
#define CONVERT_MODE_MASK 0x00018000
#define DUAL_BYTE_EN_OFFSET 14
#define DUAL_BYTE_EN_MASK 0x00004000
#define BURST_LEN_SHD_OFFSET 8
#define BURST_LEN_SHD_MASK 0x00003F00
#define LT_DS_EN_SHD_OFFSET 7
#define LT_DS_EN_SHD_MASK 0x00000080
#define RAW12_EN_SHD_OFFSET 6
#define RAW12_EN_SHD_MASK 0x00000040
#define FRAME_EN_RF_SHD_OFFSET 5
#define FRAME_EN_RF_SHD_MASK 0x00000020
#define RAW_Y_EN_SHD_OFFSET 4
#define RAW_Y_EN_SHD_MASK 0x00000010
#define LUMA_CTRL_SHD_OFFSET 2
#define LUMA_CTRL_SHD_MASK 0x0000000C
#define CROP_EN_SHD_OFFSET 1
#define CROP_EN_SHD_MASK 0x00000002
#define DVP_EN_SHD_OFFSET 0
#define DVP_EN_SHD_MASK 0x00000001

//-----------------------------------
#define CFG_SOURCE_CFG_ADDR 0x04
#define CFG_CROP_ROW_END_OFFSET 14
#define CFG_CROP_ROW_END_MASK 0x00004000
#define ONE_FRAME_EN_P_OFFSET 13
#define ONE_FRAME_EN_P_MASK 0x00002000
#define CFG_BIN_RAM_FULL_OFFSET 12
#define CFG_BIN_RAM_FULL_MASK 0x00001000
#define FRAME_SRC_MODE_OFFSET 10
#define FRAME_SRC_MODE_MASK 0x00000C00
#define SRC_SEL_OFFSET 8
#define SRC_SEL_MASK 0x00000300
#define BIT_EDIAN_OFFSET 7
#define BIT_EDIAN_MASK 0x00000080
#define SOURCE_EDIAN_OFFSET 6
#define SOURCE_EDIAN_MASK 0x00000040
#define DWIDTH_OFFSET 4
#define DWIDTH_MASK 0x00000030
#define DVP_SLOW_MODE_OFFSET 3
#define DVP_SLOW_MODE_MASK 0x00000008
#define DTYPE_OFFSET 0
#define DTYPE_MASK 0x00000007

//-----------------------------------
#define CFG_DES_CFG_ADDR 0x08
#define CFG_FRAME_END_DISB_OFFSET 28
#define CFG_FRAME_END_DISB_MASK 0x10000000
#define FRAME_END_CNT_RF_OFFSET 20
#define FRAME_END_CNT_RF_MASK 0x0FF00000
#define LUMA_THSOLD_OFFSET 8
#define LUMA_THSOLD_MASK 0x000FFF00
#define EMC_ADDR_FLAG_OFFSET 2
#define EMC_ADDR_FLAG_MASK 0x00000004
#define DES_CFG_SHD_OFFSET 0
#define DES_CFG_SHD_MASK 0x00000003

//-----------------------------------
#define CFG_CROP_CFG0_ADDR 0x0C
#define CROP_Y0_SHD_OFFSET 16
#define CROP_Y0_SHD_MASK 0x07FF0000
#define CROP_X0_SHD_OFFSET 0
#define CROP_X0_SHD_MASK 0x000007FF

//-----------------------------------
#define CFG_CROP_CFG1_ADDR 0x10
#define CROP_Y1_SHD_OFFSET 16
#define CROP_Y1_SHD_MASK 0x07FF0000
#define CROP_X1_SHD_OFFSET 0
#define CROP_X1_SHD_MASK 0x000007FF

//-----------------------------------
#define CFG_DS_CFG_ADDR 0x14
#define DST_VIRTUAL_WIDTH_OFFSET 16
#define DST_VIRTUAL_WIDTH_MASK 0xFFFF0000
#define DST_ROW_OFFSET_OFFSET 8
#define DST_ROW_OFFSET_MASK 0x0000FF00
#define Y_RATIO_SHD_OFFSET 3
#define Y_RATIO_SHD_MASK 0x00000038
#define X_RATIO_SHD_OFFSET 0
#define X_RATIO_SHD_MASK 0x00000007

//-----------------------------------
#define CFG_START_ADDR0_ADDR 0x18
#define START_ADDR0_OFFSET 0
#define START_ADDR0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_ADDR1_ADDR 0x1C
#define START_ADDR1_OFFSET 0
#define START_ADDR1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_ADDR2_ADDR 0x20
#define START_ADDR2_OFFSET 0
#define START_ADDR2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RAW_ROW_CNT_ADDR 0x24
#define BINA_FRM_DONE_CNT_OFFSET 16
#define BINA_FRM_DONE_CNT_MASK 0xFFFF0000
#define RAW_ROW_CNT_SHD_OFFSET 0
#define RAW_ROW_CNT_SHD_MASK 0x00000FFF

//-----------------------------------
#define CFG_RAW_COL_CNT_ADDR 0x28
#define RAW_COL_CNT_SHD_OFFSET 0
#define RAW_COL_CNT_SHD_MASK 0x00000FFF

//-----------------------------------
#define CFG_DIN_FIFO_CTRL_ADDR 0x2c
#define DIN_FIFO_CLR_R_OFFSET 2
#define DIN_FIFO_CLR_R_MASK 0x00000004
#define DIN_FIFO_CLR_W_OFFSET 1
#define DIN_FIFO_CLR_W_MASK 0x00000002
#define DIN_FIFO_SYNC_EN_OFFSET 0
#define DIN_FIFO_SYNC_EN_MASK 0x00000001

//-----------------------------------
#define CFG_DIN_FIFO_ST_ADDR 0x30
#define DIN_FIFO_CNT_R_OFFSET 7
#define DIN_FIFO_CNT_R_MASK 0x00000F80
#define DIN_FIFO_CNT_W_OFFSET 2
#define DIN_FIFO_CNT_W_MASK 0x0000007C
#define DIN_FIFO_EMPTY_OFFSET 1
#define DIN_FIFO_EMPTY_MASK 0x00000002
#define DIN_FIFO_FULL_OFFSET 0
#define DIN_FIFO_FULL_MASK 0x00000001

//-----------------------------------
#define CFG_MASTER_BUFFER_CTL_ADDR 0x34
#define BUFFER2_CLR_R_OFFSET 5
#define BUFFER2_CLR_R_MASK 0x00000020
#define BUFFER2_CLR_W_OFFSET 4
#define BUFFER2_CLR_W_MASK 0x00000010
#define BUFFER1_CLR_R_OFFSET 3
#define BUFFER1_CLR_R_MASK 0x00000008
#define BUFFER1_CLR_W_OFFSET 2
#define BUFFER1_CLR_W_MASK 0x00000004
#define BUFFER0_CLR_R_OFFSET 1
#define BUFFER0_CLR_R_MASK 0x00000002
#define BUFFER0_CLR_W_OFFSET 0
#define BUFFER0_CLR_W_MASK 0x00000001

//-----------------------------------
#define CFG_MASTER_BUFFER_ST_ADDR 0x38
#define BUFFER2_FULL_OFFSET 5
#define BUFFER2_FULL_MASK 0x00000020
#define BUFFER2_EMPTY_OFFSET 4
#define BUFFER2_EMPTY_MASK 0x00000010
#define BUFFER1_FULL_OFFSET 3
#define BUFFER1_FULL_MASK 0x00000008
#define BUFFER1_EMPTY_OFFSET 2
#define BUFFER1_EMPTY_MASK 0x00000004
#define BUFFER0_FULL_OFFSET 1
#define BUFFER0_FULL_MASK 0x00000002
#define BUFFER0_EMPTY_OFFSET 0
#define BUFFER0_EMPTY_MASK 0x00000001

//-----------------------------------
#define CFG_DVP_FIFO_ST_ADDR 0x3c
#define DVP_FIFO2_FULL_OFFSET 5
#define DVP_FIFO2_FULL_MASK 0x00000020
#define DVP_FIFO2_EMPTY_OFFSET 4
#define DVP_FIFO2_EMPTY_MASK 0x00000010
#define DVP_FIFO1_FULL_OFFSET 3
#define DVP_FIFO1_FULL_MASK 0x00000008
#define DVP_FIFO1_EMPTY_OFFSET 2
#define DVP_FIFO1_EMPTY_MASK 0x00000004
#define DVP_FIFO0_FULL_OFFSET 1
#define DVP_FIFO0_FULL_MASK 0x00000002
#define DVP_FIFO0_EMPTY_OFFSET 0
#define DVP_FIFO0_EMPTY_MASK 0x00000001

//-----------------------------------
#define CFG_DVP_INT_RAW_ADDR 0x40
#define DVP_INT_RAW_OFFSET 0
#define DVP_INT_RAW_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DVP_INT_STS_ADDR 0x44
#define DVP_INT_STS_OFFSET 0
#define DVP_INT_STS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DVP_INT_ENA_ADDR 0x48
#define DVP_INT_ENA_OFFSET 0
#define DVP_INT_ENA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DVP_INT_CLR_ADDR 0x4c
#define DVP_INT_CLR_OFFSET 0
#define DVP_INT_CLR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DVP_SHDOW_CTRL_ADDR 0x50
#define BINA_FACTOR_SHD_OFFSET 6
#define BINA_FACTOR_SHD_MASK 0x00000040
#define BINA_CTRL_SHD_OFFSET 5
#define BINA_CTRL_SHD_MASK 0x00000020
#define DS_CFG_SHD_OFFSET 4
#define DS_CFG_SHD_MASK 0x00000010
#define RAW_CNT_SHD_OFFSET 3
#define RAW_CNT_SHD_MASK 0x00000008
#define CROP_CFG_SHD_OFFSET 2
#define CROP_CFG_SHD_MASK 0x00000004
#define DES_SEL_SHD_OFFSET 1
#define DES_SEL_SHD_MASK 0x00000002
#define DCAM_CTRL_SHD_OFFSET 0
#define DCAM_CTRL_SHD_MASK 0x00000001

//-----------------------------------
#define CFG_BINA_CTRL_ADDR 0x54
#define CFG_BINA_WR_END_OFFSET 5
#define CFG_BINA_WR_END_MASK 0x00000020
#define TRANSPOSE_EN_SHD_OFFSET 3
#define TRANSPOSE_EN_SHD_MASK 0x00000018
#define BINA_BLOCK_SEL_SHD_OFFSET 2
#define BINA_BLOCK_SEL_SHD_MASK 0x00000004
#define BINA_STORE_SEL_SHD_OFFSET 1
#define BINA_STORE_SEL_SHD_MASK 0x00000002
#define BINA_EN_SHD_OFFSET 0
#define BINA_EN_SHD_MASK 0x00000001

//-----------------------------------
#define CFG_BINA_FACTOR_ADDR 0x58
#define BINA_C2_SHD_OFFSET 16
#define BINA_C2_SHD_MASK 0x00070000
#define BINA_C1_SHD_OFFSET 8
#define BINA_C1_SHD_MASK 0x0000FF00
#define BINA_THOSD_SHD_OFFSET 0
#define BINA_THOSD_SHD_MASK 0x000000FF

//-----------------------------------
#define CFG_BINA_DS_ADDR 0x5c
#define BINA_Y_DS_SHD_OFFSET 4
#define BINA_Y_DS_SHD_MASK 0x00000010
#define BINA_X_DS_SHD_OFFSET 2
#define BINA_X_DS_SHD_MASK 0x0000000C
#define BINA_Y_PRE_DS_SHD_OFFSET 1
#define BINA_Y_PRE_DS_SHD_MASK 0x00000002
#define BINA_X_PRE_DS_SHD_OFFSET 0
#define BINA_X_PRE_DS_SHD_MASK 0x00000001

//-----------------------------------
#define CFG_BINA_AEC_ADDR 0x60
#define AEC_REG_CLR_OFFSET 4
#define AEC_REG_CLR_MASK 0x00000010
#define AEC_CROP_EN_OFFSET 3
#define AEC_CROP_EN_MASK 0x00000008
#define BINA_AEC_Y_DS_OFFSET 2
#define BINA_AEC_Y_DS_MASK 0x00000004
#define BINA_AEC_X_DS_OFFSET 1
#define BINA_AEC_X_DS_MASK 0x00000002
#define BINA_AEC_EN_RF_OFFSET 0
#define BINA_AEC_EN_RF_MASK 0x00000001

//-----------------------------------
#define CFG_BINA_AEC00_ADDR 0x64
#define AEC_REG00_OFFSET 0
#define AEC_REG00_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC01_ADDR 0x68
#define AEC_REG01_OFFSET 0
#define AEC_REG01_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC02_ADDR 0x6c
#define AEC_REG02_OFFSET 0
#define AEC_REG02_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC03_ADDR 0x70
#define AEC_REG03_OFFSET 0
#define AEC_REG03_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC10_ADDR 0x74
#define AEC_REG10_OFFSET 0
#define AEC_REG10_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC11_ADDR 0x78
#define AEC_REG11_OFFSET 0
#define AEC_REG11_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC12_ADDR 0x7c
#define AEC_REG12_OFFSET 0
#define AEC_REG12_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC13_ADDR 0x80
#define AEC_REG13_OFFSET 0
#define AEC_REG13_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC20_ADDR 0x84
#define AEC_REG20_OFFSET 0
#define AEC_REG20_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC21_ADDR 0x88
#define AEC_REG21_OFFSET 0
#define AEC_REG21_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC22_ADDR 0x8c
#define AEC_REG22_OFFSET 0
#define AEC_REG22_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC23_ADDR 0x90
#define AEC_REG23_OFFSET 0
#define AEC_REG23_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC30_ADDR 0x94
#define AEC_REG30_OFFSET 0
#define AEC_REG30_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC31_ADDR 0x98
#define AEC_REG31_OFFSET 0
#define AEC_REG31_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC32_ADDR 0x9c
#define AEC_REG32_OFFSET 0
#define AEC_REG32_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BINA_AEC33_ADDR 0xa0
#define AEC_REG33_OFFSET 0
#define AEC_REG33_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_LT_DS_CTRL_ADDR 0xa4
#define V_RATIO_INT_OFFSET 24
#define V_RATIO_INT_MASK 0x07000000
#define V_RATIO_FRACT_OFFSET 16
#define V_RATIO_FRACT_MASK 0x00FF0000
#define H_RATIO_INT_OFFSET 8
#define H_RATIO_INT_MASK 0x00000700
#define H_RATIO_FRACT_OFFSET 0
#define H_RATIO_FRACT_MASK 0x000000FF

//-----------------------------------
#define CFG_MIPI_SEL_ADDR 0xa8
#define CSI_SOFT_RST_OFFSET 2
#define CSI_SOFT_RST_MASK 0x00000004
#define CSI_RX_SEL_OFFSET 0
#define CSI_RX_SEL_MASK 0x00000003

//-----------------------------------
#define CFG_AEC_CROP_CFG0_ADDR 0xac
#define AEC_CROP_Y0_OFFSET 16
#define AEC_CROP_Y0_MASK 0x07FF0000
#define AEC_CROP_X0_OFFSET 0
#define AEC_CROP_X0_MASK 0x000007FF

//-----------------------------------
#define CFG_AEC_CROP_CFG1_ADDR 0xb0
#define AEC_CROP_Y1_OFFSET 16
#define AEC_CROP_Y1_MASK 0x07FF0000
#define AEC_CROP_X1_OFFSET 0
#define AEC_CROP_X1_MASK 0x000007FF

//-----------------------------------
#define CFG_BINA_FRAME_ADDR_ADDR 0xb4
#define FRAME_ADDR_SW_OFFSET 16
#define FRAME_ADDR_SW_MASK 0x00010000
#define FRAME_END_ADDR_RF_OFFSET 0
#define FRAME_END_ADDR_RF_MASK 0x00007FFF

//-----------------------------------
#define CFG_BINA_BLOCK_CFG_ADDR 0xb8
#define BLOCK1_SW_CFG_OFFSET 17
#define BLOCK1_SW_CFG_MASK 0x00020000
#define BLOCK0_SW_CFG_OFFSET 16
#define BLOCK0_SW_CFG_MASK 0x00010000
#define LINE_BLOCK1_RF_OFFSET 8
#define LINE_BLOCK1_RF_MASK 0x00007F00
#define LINE_BLOCK0_RF_OFFSET 0
#define LINE_BLOCK0_RF_MASK 0x0000007F

//-----------------------------------
#define CFG_RESERVE_ADDR 0xbc
#define RESERVE_OFFSET 0
#define RESERVE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GAMMA_COEF0_ADDR 0xc0
#define REGION1_ADD_OFFSET 24
#define REGION1_ADD_MASK 0xFF000000
#define REGION1_MUL_OFFSET 16
#define REGION1_MUL_MASK 0x00FF0000
#define REGION0_ADD_OFFSET 8
#define REGION0_ADD_MASK 0x0000FF00
#define REGION0_MUL_OFFSET 0
#define REGION0_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF1_ADDR 0xc4
#define REGION3_ADD_OFFSET 24
#define REGION3_ADD_MASK 0xFF000000
#define REGION3_MUL_OFFSET 16
#define REGION3_MUL_MASK 0x00FF0000
#define REGION2_ADD_OFFSET 8
#define REGION2_ADD_MASK 0x0000FF00
#define REGION2_MUL_OFFSET 0
#define REGION2_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF2_ADDR 0xc8
#define REGION5_ADD_OFFSET 24
#define REGION5_ADD_MASK 0xFF000000
#define REGION5_MUL_OFFSET 16
#define REGION5_MUL_MASK 0x00FF0000
#define REGION4_ADD_OFFSET 8
#define REGION4_ADD_MASK 0x0000FF00
#define REGION4_MUL_OFFSET 0
#define REGION4_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF3_ADDR 0xcc
#define REGION7_ADD_OFFSET 24
#define REGION7_ADD_MASK 0xFF000000
#define REGION7_MUL_OFFSET 16
#define REGION7_MUL_MASK 0x00FF0000
#define REGION6_ADD_OFFSET 8
#define REGION6_ADD_MASK 0x0000FF00
#define REGION6_MUL_OFFSET 0
#define REGION6_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF4_ADDR 0xd0
#define REGION9_ADD_OFFSET 24
#define REGION9_ADD_MASK 0xFF000000
#define REGION9_MUL_OFFSET 16
#define REGION9_MUL_MASK 0x00FF0000
#define REGION8_ADD_OFFSET 8
#define REGION8_ADD_MASK 0x0000FF00
#define REGION8_MUL_OFFSET 0
#define REGION8_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF5_ADDR 0xd4
#define REGION11_ADD_OFFSET 24
#define REGION11_ADD_MASK 0xFF000000
#define REGION11_MUL_OFFSET 16
#define REGION11_MUL_MASK 0x00FF0000
#define REGION10_ADD_OFFSET 8
#define REGION10_ADD_MASK 0x0000FF00
#define REGION10_MUL_OFFSET 0
#define REGION10_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF6_ADDR 0xd8
#define REGION13_ADD_OFFSET 24
#define REGION13_ADD_MASK 0xFF000000
#define REGION13_MUL_OFFSET 16
#define REGION13_MUL_MASK 0x00FF0000
#define REGION12_ADD_OFFSET 8
#define REGION12_ADD_MASK 0x0000FF00
#define REGION12_MUL_OFFSET 0
#define REGION12_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF7_ADDR 0xdc
#define REGION15_ADD_OFFSET 24
#define REGION15_ADD_MASK 0xFF000000
#define REGION15_MUL_OFFSET 16
#define REGION15_MUL_MASK 0x00FF0000
#define REGION14_ADD_OFFSET 8
#define REGION14_ADD_MASK 0x0000FF00
#define REGION14_MUL_OFFSET 0
#define REGION14_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF8_ADDR 0xe0
#define REGION17_ADD_OFFSET 24
#define REGION17_ADD_MASK 0xFF000000
#define REGION17_MUL_OFFSET 16
#define REGION17_MUL_MASK 0x00FF0000
#define REGION16_ADD_OFFSET 8
#define REGION16_ADD_MASK 0x0000FF00
#define REGION16_MUL_OFFSET 0
#define REGION16_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF9_ADDR 0xe4
#define REGION19_ADD_OFFSET 24
#define REGION19_ADD_MASK 0xFF000000
#define REGION19_MUL_OFFSET 16
#define REGION19_MUL_MASK 0x00FF0000
#define REGION18_ADD_OFFSET 8
#define REGION18_ADD_MASK 0x0000FF00
#define REGION18_MUL_OFFSET 0
#define REGION18_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_GAMMA_COEF10_ADDR 0xe8
#define REGION20_ADD_OFFSET 8
#define REGION20_ADD_MASK 0x0000FF00
#define REGION20_MUL_OFFSET 0
#define REGION20_MUL_MASK 0x000000FF

//-----------------------------------
#define CFG_SRC_CROP_CFG0_ADDR 0xec
#define SRC_CROP_Y0_OFFSET 16
#define SRC_CROP_Y0_MASK 0x07FF0000
#define SRC_CROP_X0_OFFSET 0
#define SRC_CROP_X0_MASK 0x000007FF

//-----------------------------------
#define CFG_SRC_CROP_CFG1_ADDR 0xf0
#define SRC_CROP_Y1_OFFSET 16
#define SRC_CROP_Y1_MASK 0x07FF0000
#define SRC_CROP_X1_OFFSET 0
#define SRC_CROP_X1_MASK 0x000007FF

//-----------------------------------
#define CFG_SRC_FRAME_CTRL_ADDR 0xf4
#define CFG_HBLANK_CNT_OFFSET 8
#define CFG_HBLANK_CNT_MASK 0x00FFFF00
#define SRC_BURST_LEN_OFFSET 2
#define SRC_BURST_LEN_MASK 0x000000FC
#define SRC_PIEXL_WIDTH_OFFSET 1
#define SRC_PIEXL_WIDTH_MASK 0x00000002
#define EMC_FRAME_EN_OFFSET 0
#define EMC_FRAME_EN_MASK 0x00000001

//-----------------------------------
#define CFG_SRC_START_ADDR_ADDR 0xf8
#define SRC_START_ADDR_OFFSET 0
#define SRC_START_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SRC_ADDR_CFG_ADDR 0xfc
#define SRC_VIRTUAL_WIDTH_OFFSET 8
#define SRC_VIRTUAL_WIDTH_MASK 0x00FFFF00
#define SRC_ROW_OFFSET_OFFSET 0
#define SRC_ROW_OFFSET_MASK 0x000000FF

//-----------------------------------
#define CFG_RAW_Y_RAM_CFG_ADDR 0x100
#define DATA_IN_CNT_OFFSET 16
#define DATA_IN_CNT_MASK 0xFFFF0000
#define DBG_SEL_OFFSET 8
#define DBG_SEL_MASK 0x0000FF00
#define Y_RAM_CNT_RF_OFFSET 4
#define Y_RAM_CNT_RF_MASK 0x000000F0
#define DBG_CHN_SEL_OFFSET 2
#define DBG_CHN_SEL_MASK 0x0000000C
#define RAW_Y_RAM_FULL_OFFSET 1
#define RAW_Y_RAM_FULL_MASK 0x00000002
#define RAW_Y_RAM_EN_P_OFFSET 0
#define RAW_Y_RAM_EN_P_MASK 0x00000001

//-----------------------------------
#define CFG_LOW_SPEED_DVP_CFG_ADDR 0x104
#define DLY_SEL6_OFFSET 24
#define DLY_SEL6_MASK 0x0F000000
#define DLY_SEL5_OFFSET 20
#define DLY_SEL5_MASK 0x00F00000
#define DLY_SEL4_OFFSET 16
#define DLY_SEL4_MASK 0x000F0000
#define DLY_SEL3_OFFSET 12
#define DLY_SEL3_MASK 0x0000F000
#define DLY_SEL2_OFFSET 8
#define DLY_SEL2_MASK 0x00000F00
#define DLY_SEL1_OFFSET 4
#define DLY_SEL1_MASK 0x000000F0
#define DLY_SEL0_OFFSET 0
#define DLY_SEL0_MASK 0x0000000F

//-----------------------------------
#define CFG_DVP_DBG0_ADDR 0x108
#define DBG_BUS_OFFSET 0
#define DBG_BUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_ADDR3_ADDR 0x10c
#define START_ADDR3_OFFSET 0
#define START_ADDR3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_ADDR4_ADDR 0x110
#define START_ADDR4_OFFSET 0
#define START_ADDR4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_ADDR5_ADDR 0x114
#define START_ADDR5_OFFSET 0
#define START_ADDR5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL0_ADDR 0x118
#define FRAME_AEC_EN_RF_OFFSET 17
#define FRAME_AEC_EN_RF_MASK 0x00020000
#define FRAME_CAL_EN_RF_OFFSET 16
#define FRAME_CAL_EN_RF_MASK 0x00010000
#define DATA2_MIN_OFFSET 8
#define DATA2_MIN_MASK 0x0000FF00
#define DATA2_MAX_OFFSET 0
#define DATA2_MAX_MASK 0x000000FF

//-----------------------------------
#define CFG_FRAME_CAL1_ADDR 0x11c
#define DATA1_MIN_OFFSET 24
#define DATA1_MIN_MASK 0xFF000000
#define DATA1_MAX_OFFSET 16
#define DATA1_MAX_MASK 0x00FF0000
#define DATA0_MIN_OFFSET 8
#define DATA0_MIN_MASK 0x0000FF00
#define DATA0_MAX_OFFSET 0
#define DATA0_MAX_MASK 0x000000FF

//-----------------------------------
#define CFG_FRAME_CAL2_ADDR 0x120
#define DATA0_SUM_OFFSET 0
#define DATA0_SUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL3_ADDR 0x124
#define DATA1_SUM_OFFSET 0
#define DATA1_SUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL4_ADDR 0x128
#define DATA2_SUM_OFFSET 0
#define DATA2_SUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL5_ADDR 0x12c
#define DATA0_SUQARE_L_OFFSET 0
#define DATA0_SUQARE_L_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL6_ADDR 0x130
#define DATA1_SUQARE_L_OFFSET 0
#define DATA1_SUQARE_L_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL7_ADDR 0x134
#define DATA2_SUQARE_L_OFFSET 0
#define DATA2_SUQARE_L_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_FRAME_CAL8_ADDR 0x138
#define DATA2_SUQARE_H_OFFSET 16
#define DATA2_SUQARE_H_MASK 0x001F0000
#define DATA1_SUQARE_H_OFFSET 8
#define DATA1_SUQARE_H_MASK 0x00001F00
#define DATA0_SUQARE_H_OFFSET 0
#define DATA0_SUQARE_H_MASK 0x0000001F

//HW module read/write macro
#define DVP_RF0_READ_REG(addr) SOC_READ_REG(DVP_RF0_BASEADDR + addr)
#define DVP_RF0_WRITE_REG(addr,value) SOC_WRITE_REG(DVP_RF0_BASEADDR + addr,value)
#define DVP_RF1_READ_REG(addr) SOC_READ_REG(DVP_RF1_BASEADDR + addr)
#define DVP_RF1_WRITE_REG(addr,value) SOC_WRITE_REG(DVP_RF1_BASEADDR + addr,value)
#define DVP_RF2_READ_REG(addr) SOC_READ_REG(DVP_RF2_BASEADDR + addr)
#define DVP_RF2_WRITE_REG(addr,value) SOC_WRITE_REG(DVP_RF2_BASEADDR + addr,value)
#define DVP_RF3_READ_REG(addr) SOC_READ_REG(DVP_RF3_BASEADDR + addr)
#define DVP_RF3_WRITE_REG(addr,value) SOC_WRITE_REG(DVP_RF3_BASEADDR + addr,value)