64 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			64 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
|  | 
 | ||
|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL0_ADDR 0x000
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|  | #define CHOL_NUM_OPERATION_OFFSET 16
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|  | #define CHOL_NUM_OPERATION_MASK 0xFFFF0000
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|  | #define CHOL_FP_RND_OFFSET 8
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|  | #define CHOL_FP_RND_MASK 0x00000700
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|  | #define CHOL_OP_TYPE_OFFSET 4
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|  | #define CHOL_OP_TYPE_MASK 0x00000030
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|  | #define CHOL_FORCE_ON_OFFSET 3
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|  | #define CHOL_FORCE_ON_MASK 0x00000008
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|  | #define CHOL_MATRIX_SIZE_OFFSET 0
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|  | #define CHOL_MATRIX_SIZE_MASK 0x00000007
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL1_ADDR 0x004
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|  | #define CHOL_SRC_START_ADDRESS_OFFSET 0
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|  | #define CHOL_SRC_START_ADDRESS_MASK 0xFFFFFFFF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL2_ADDR 0x008
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|  | #define CHOL_SRC_SIZE_OFFSET 0
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|  | #define CHOL_SRC_SIZE_MASK 0x000000FF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL3_ADDR 0x00C
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|  | #define CHOL_INV_START_ADDRESS_OFFSET 0
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|  | #define CHOL_INV_START_ADDRESS_MASK 0xFFFFFFFF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL4_ADDR 0x010
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|  | #define CHOL_DET_START_ADDRESS_OFFSET 0
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|  | #define CHOL_DET_START_ADDRESS_MASK 0xFFFFFFFF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_CTRL5_ADDR 0x014
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|  | #define CHOL_FP_OP_ERR_MASK_OFFSET 0
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|  | #define CHOL_FP_OP_ERR_MASK_MASK 0x000000FF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_START_ADDR 0x018
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|  | #define CHOL_CHOL_START_TRIG_OFFSET 0
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|  | #define CHOL_CHOL_START_TRIG_MASK 0x00000001
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_STATUS_ADDR 0x01C
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|  | #define CHOL_CHOL_DONE_OFFSET 31
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|  | #define CHOL_CHOL_DONE_MASK 0x80000000
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|  | #define CHOL_FP_OP_STATUS_OFFSET 16
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|  | #define CHOL_FP_OP_STATUS_MASK 0x00FF0000
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|  | #define CHOL_CHOL_COMPLETE_COUNT_OFFSET 0
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|  | #define CHOL_CHOL_COMPLETE_COUNT_MASK 0x0000FFFF
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|  | 
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|  | //-----------------------------------
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|  | #define CFG_CHOL_CHOL_INT_CLR_ADDR 0x020
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|  | #define CHOL_CHOL_INT_CLR_OFFSET 0
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|  | #define CHOL_CHOL_INT_CLR_MASK 0x00000001
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|  | 
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|  | //HW module read/write macro
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|  | #define RGF_CHOL0_READ_REG(addr) SOC_READ_REG(RGF_CHOL0_BASEADDR + addr)
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|  | #define RGF_CHOL0_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CHOL0_BASEADDR + addr,value)
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|  | #define RGF_CHOL1_READ_REG(addr) SOC_READ_REG(RGF_CHOL1_BASEADDR + addr)
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|  | #define RGF_CHOL1_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CHOL1_BASEADDR + addr,value)
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