kunlun/plc/halmac/hw3/zc/mac_zc_hw.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "mac_sys_reg.h"
#include "hw_reg_api.h"
#include "os_types.h"
#include "os_mem_api.h"
#include "plc_protocol.h"
#include "iot_config_api.h"
#include "iot_utils_api.h"
#include "iot_io_api.h"
#include "mac_zc_hw.h"

#if MAC_ZC_ENABLE

void mac_zc_hw_cap_enable_set(uint8_t cap_id, uint8_t is_ena)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
        * cap_id) + CFG_ZC0_CAP_CTRL_ADDR;

    tmp = RGF_MAC_READ_REG(reg_addr);
    REG_FIELD_SET(CFG_ZC0_CAP_ENABLE, tmp, !!is_ena);
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void mac_zc_hw_cap_intr_num_set(uint8_t cap_id, uint8_t num)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
        * cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);
    REG_FIELD_SET(CFG_ZC0_CAP_NUM, tmp, num);
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void mac_zc_hw_cap_sample_num_set(uint8_t cap_id, uint8_t num)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
        * cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);
    REG_FIELD_SET(CFG_ZC0_CAP_INTERVAL, tmp, num);
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void mac_zc_hw_cap_in_sel_set(uint8_t cap_id, uint8_t in_sel)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
        * cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);
    REG_FIELD_SET(CFG_ZC0_IN_SEL, tmp, !!in_sel);
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void mac_zc_hw_cap_edge_set(uint8_t cap_id, uint8_t is_fall_edge)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_CTRL_ADDR - CFG_ZC0_CAP_CTRL_ADDR)
        * cap_id) + CFG_ZC0_CAP_CTRL_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);
    if (is_fall_edge) {
        REG_FIELD_SET(CFG_ZC0_EDGE_SEL, tmp, 1);
    } else {
        REG_FIELD_SET(CFG_ZC0_EDGE_SEL, tmp, 0);
    }
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void mac_zc_hw_cap_filter_set(uint8_t cap_id, uint16_t high, uint16_t low)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_SOLID_ADDR - CFG_ZC0_CAP_SOLID_ADDR)
        * cap_id) + CFG_ZC0_CAP_SOLID_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);
    REG_FIELD_SET(CFG_ZC0_SOLID_HIGH_CNT, tmp, high);
    REG_FIELD_SET(CFG_ZC0_SOLID_LOW_CNT, tmp, low);
    RGF_MAC_WRITE_REG(reg_addr, tmp);
}

void IRAM_ATTR mac_zc_hw_cap_data_num_get(uint32_t cap_id, uint8_t *ntb_num,
    uint8_t *lts_num)
{
    uint32_t tmp;
    uint32_t reg_addr;

    reg_addr = ((CFG_ZC1_CAP_FIFO_STS_ADDR - CFG_ZC0_CAP_FIFO_STS_ADDR)
        * cap_id) + CFG_ZC0_CAP_FIFO_STS_ADDR;
    tmp = RGF_MAC_READ_REG(reg_addr);

    if (ntb_num) {
        *ntb_num = (uint8_t)REG_FIELD_GET(CFG_RO_NTB_ZC0_FIFO_DATA_NUM, tmp);
    }

    if (lts_num) {
        *lts_num = (uint8_t)REG_FIELD_GET(CFG_RO_LOCAL_ZC0_FIFO_DATA_NUM, tmp);
    }
}

uint8_t IRAM_ATTR mac_zc_hw_cap_ntb_read(uint8_t cap_id, uint8_t num,
    uint32_t *buf)
{
    uint8_t idx, cnt = 0;
    uint32_t r_addr, tmp;

    r_addr = ((CFG_NTB_ZC1_CAP_FIFO_DATA_ADDR
        - CFG_NTB_ZC0_CAP_FIFO_DATA_ADDR) * cap_id)
        + CFG_NTB_ZC0_CAP_FIFO_DATA_ADDR;

    mac_zc_hw_cap_data_num_get(cap_id, &cnt, NULL);

    cnt = min(cnt, num);
    for (idx = 0; idx < cnt; idx++) {
        tmp = RGF_MAC_READ_REG(r_addr);
        if (buf) {
            buf[idx] = tmp;
        }
    }

    return cnt;
}

uint8_t IRAM_ATTR mac_zc_hw_cap_lts_read(uint8_t cap_id, uint8_t num,
    uint32_t *buf)
{
    uint8_t idx, cnt = 0;
    uint32_t r_addr, tmp;

    r_addr = ((CFG_LOCAL_ZC1_CAP_FIFO_DATA_ADDR
        - CFG_LOCAL_ZC0_CAP_FIFO_DATA_ADDR) * cap_id)
        + CFG_LOCAL_ZC0_CAP_FIFO_DATA_ADDR;

    mac_zc_hw_cap_data_num_get(cap_id, NULL, &cnt);

    cnt = min(cnt, num);
    for (idx = 0; idx < cnt; idx++) {
        tmp = RGF_MAC_READ_REG(r_addr);
        if (buf) {
            buf[idx] = tmp;
        }
    }

    return cnt;
}

void mac_zc_hw_cap_data_clr(uint8_t cap_id)
{
    mac_zc_hw_cap_ntb_read(cap_id, MAC_ZC_HW_CAP_BUF_DEPTH, NULL);
    mac_zc_hw_cap_lts_read(cap_id, MAC_ZC_HW_CAP_BUF_DEPTH, NULL);
}

/* init zc hw */
void mac_zc_hw_init(uint8_t is_half_collect, uint8_t cap_edge)
{
    uint8_t id;

    /* for kl3 hw support only falling or rising edge collect, not support half
     * period collect.
     * kl3 chip contains 6 zc capture hw, every 2 zc capture hw can support
     * 1 phase zero crossing collect. One zc capture hw collects the rising edge
     * of the PLC line, and the other zc capture hw collects the falling edge
     * of the PLC line. Both rising and falling edges of the PLC line are
     * converted to the same pulse signal by board hardware.
     */
    (void)is_half_collect;

    cap_edge = (MAC_ZC_HW_CAP_EDGE_FALL == cap_edge) ? 1 : 0;

    for (id = MAC_ZC_HW_CAP0; id < MAC_ZC_HW_CAP_CNT; id++) {
        mac_zc_hw_cap_filter_set(id, MAC_ZC_HW_FILTER_HIGH_CNT,
            MAC_ZC_HW_FILTER_LOW_CNT);
        mac_zc_hw_cap_intr_num_set(id, 1);
        mac_zc_hw_cap_sample_num_set(id, 1);
        mac_zc_hw_cap_in_sel_set(id, 0);
        mac_zc_hw_cap_edge_set(id, cap_edge);
    }
}

#endif