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kunlun/plc/halphy/hw/inc/phy_phase.h

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2024-09-28 14:24:04 +08:00
/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
***************************************************************************/
#ifndef __PHY_PHASE_H
#define __PHY_PHASE_H
#include "iot_config.h"
#include "os_types.h"
#include "phy_bb.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PHY_PHASE_OVR_ALL = 0,
PHY_PHASE_OVR_A = 1,
PHY_PHASE_OVR_B = 2,
PHY_PHASE_OVR_C = 3
} PHY_PHASE_OVR_ID;
typedef enum {
PHY_TXRX_OVR_IDLE,
PHY_TXRX_OVR_RX,
PHY_TXRX_OVR_TX,
PHY_TXRX_OVR_TXRX
} PHY_TXRX_OVR_ID;
#if K48_CCO_MULTI_CHANNEL_SELECT_ENABLE
#define TX_EN_CMB_A (3 << 0)
#define RX_EN_CMB_A (3 << 0)
#define TX_EN_CMB_B (3 << 2)
#define RX_EN_CMB_B (3 << 2)
#define TX_EN_CMB_C (3 << 4)
#define RX_EN_CMB_C (3 << 4)
#else
#define TX_EN_CMB_A (1 << 0)
#define RX_EN_CMB_A (1 << 1)
#define TX_EN_CMB_B (1 << 2)
#define RX_EN_CMB_B (1 << 3)
#define TX_EN_CMB_C (1 << 4)
#define RX_EN_CMB_C (1 << 5)
#endif
/**
*@brief phy_phase_ovr_set.
*
* force phase select with A/B/C/ALL,
*
*@param phase [A,B,C,ALL]
*@param en [true/false]
*@param mode [0:idle,1:rx,2:tx,3:txrx]
*@exception [none.]
*@return [none.]
*/
void phy_phase_ovr_set(PHY_PHASE_OVR_ID phase, bool_t en, PHY_TXRX_OVR_ID mode);
/**
*@brief phy_set_phase_overwrite() - set the tx&rx descriptor(0~3) map to
* hw phase(phase A/B/C/ALL)
*
* set user protocol phase value map to kunlun chip's actual phase.
* for example:
* smart grid phase A = 1, then set desc1_to_hw_phae = HW_DESC_PHASE_A,
* since then, set descriptor's tx_phase/rx_phase = PLC_PHASE_A(1), kunlun chip
* will (tx&rx) work in phase A.
* if is_enable != false, desc0_to_hw_phase/desc1_to_hw_phase/desc2_to_hw_phase/
* desc3_to_hw_phase must be set to HW_DESC_PHASE_ALL/HW_DESC_PHASE_A/
* HW_DESC_PHASE_B/ HW_DESC_PHASE_C one of the values.
*
*@param is_enable: is enable phase overwrite.
* true - enable, false - disable
*@param desc0_to_hw_phase: tx&rx descriptor value 0 map to hw phase, this value
* must be HW_DESC_PHASE_ALL/HW_DESC_PHASE_A/
* HW_DESC_PHASE_B/HW_DESC_PHASE_C
*@param desc1_to_hw_phase: tx&rx descriptor value 1 map to hw phase, same as
* desc0_to_hw_phase.
*@param desc2_to_hw_phase: tx&rx descriptor value 2 map to hw phase, same as
* desc0_to_hw_phase.
*@param desc3_to_hw_phase: tx&rx descriptor value 3 map to hw phase, same as
* desc0_to_hw_phase.
*@return none
*/
void phy_set_phase_overwrite(bool_t is_enable,
uint8_t desc0_to_hw_phase, uint8_t desc1_to_hw_phase,
uint8_t desc2_to_hw_phase, uint8_t desc3_to_hw_phase);
/**
*@brief register_get_rx_phase_cb phy get mac rx phase cb.
*@exception [none.]
*@return [none.]
*/
void register_get_rx_phase_cb(mac_get_rx_phase_cb_t cb);
/**
*@brief phy_get_mac_rx_phase get phy callback value, rx phase.
*@exception [none.]
*@return [rx phase.]
*/
uint32_t phy_get_mac_rx_phase();
/**
*@brief phy_force_0_access_require
* require the privilage to access force 0 register.
*
*@param void [void]
*@exception [none.]
*@return [none.]
*/
void phy_force_0_access_require();
/**
*@brief phy_force_0_access_release
* release the privilage to access force 0 register.
*
*@param void [void]
*@exception [none.]
*@return [none.]
*/
void phy_force_0_access_release();
/**
*@brief phy_force_0_access_require_from_isr
* require the privilage to access force 0 register from ISR.
*
*@param void [void]
*@exception [none.]
*@return uint32_t [require the privilage success or not]
*/
void phy_force_0_access_require_from_isr();
/**
*@brief phy_force_0_access_release_from_isr
* release the privilage to access force 0 register from ISR.
*
*@param void [void]
*@exception [none.]
*@return uint32_t [release the privilage success or not]
*/
void phy_force_0_access_release_from_isr();
/**
*@brief phy_rx_phase_force_set
* force phy rx phase from mac.
*
*@param enable [true or false]
*@param hw_phase [ALL/A/B/C]
*@exception [none.]
*@return [none.]
*/
void phy_rx_phase_force_set(bool_t enable, uint8_t hw_phase);
/**
*@brief phy_rx_phase_force_set_on_dump
* force phy rx phase from mac on dump mode.
*
*@param enable [true or false]
*@param hw_phase [ALL/A/B/C]
*@exception [none.]
*@return [none.]
*/
void phy_rx_phase_force_set_on_dump(bool_t enable, uint8_t hw_phase);
/**
*@brief phy_get_rx_force_phase_val get rx force phase.
*
*@return [force phase]
*/
uint32_t phy_get_rx_force_phase_val();
/**
*@brief phy_get_rx_phase_force_en get rx force phase enable/disable.
*
*@return [0]
*/
uint32_t phy_get_rx_phase_force_en();
/**
* @brief phy_get_hw_phy_rx_phase_sel() - get phy rx phase select
*
* @param none
*
* @return phy rx phase num
*/
uint32_t phy_get_hw_phy_rx_phase_sel(void);
/**
* @brief enable/disable force phy tx
*
* @param is_enable: 0 - disable force phy tx
* 1 - enable force phy tx
*
* @return none
*/
void phy_set_tx_force_enable(uint8_t is_enable);
#ifdef __cplusplus
}
#endif
#endif