76 lines
2.3 KiB
C
76 lines
2.3 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "phy_agc.h"
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#include "iot_config.h"
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#include "iot_errno_api.h"
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#include "iot_io_api.h"
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#include "phy_dfe_reg.h"
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#include "phy_reg.h"
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#include "hw_reg_api.h"
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#include "hw_tonemask.h"
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#include "phy_tx_reg.h"
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#include "phy_txrx_pwr.h"
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#include "phy_chn.h"
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void phy_agc_adc_data_set(bool_t ena, uint8_t data)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_DFE_READ_REG(CFG_BB_AGC_SWCFG_EN_ADDR);
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REG_FIELD_SET( SW_GAIN_CFG_EN, tmp, ena );
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PHY_DFE_WRITE_REG(CFG_BB_AGC_SWCFG_EN_ADDR, tmp);
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tmp = PHY_DFE_READ_REG(CFG_GAIN_SERIAL_CFG0_ADDR);
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REG_FIELD_SET( SW_GAIN_CFG0_DATA, tmp, data << 4 );
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PHY_DFE_WRITE_REG(CFG_GAIN_SERIAL_CFG0_ADDR, tmp);
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#else
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(void)ena;
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(void)data;
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#endif
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}
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void phy_tx_pwr_ctl_en( \
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bool_t fd_en, bool_t td_en, bool_t ana_en)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_TX_READ_REG(CFG_BB_TX_PWR_FROM_MAC_CTRL_ADDR);
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REG_FIELD_SET( SW_TX_PWR_FD_FROM_TX_DESC, tmp, fd_en );
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REG_FIELD_SET( SW_TX_PWR_TD_FROM_TX_DESC, tmp, td_en );
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REG_FIELD_SET( SW_TX_PWR_ANA_FROM_TX_DESC, tmp, ana_en );
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PHY_TX_WRITE_REG(CFG_BB_TX_PWR_FROM_MAC_CTRL_ADDR, tmp);
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#else
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(void)fd_en;
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(void)td_en;
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(void)ana_en;
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#endif
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}
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void phy_gain_chg_rst_en_set(uint8_t rst)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_DFE_READ_REG(CFG_BB_DFE_RESET_CTRL_ADDR);
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REG_FIELD_SET( SW_GAIN_CHG_RST, tmp, rst );
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PHY_DFE_WRITE_REG(CFG_BB_DFE_RESET_CTRL_ADDR, tmp);
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#else
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(void)rst;
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#endif
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}
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