kunlun/plc/halphy/phy_data.c

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "hw_reg_api.h"
#include "phy_data.h"
#include "iot_config.h"
#include "phy_bb.h"
#include "phy_dfe_reg.h"
#include "phy_rxtd_reg.h"
#include "hw_tonemask.h"
#include "iot_io.h"
#include "iot_errno_api.h"
#include "mac_sys_reg.h"
#include "os_mem.h"
#include "hw_phy_api.h"
#include "phy_ana.h"
#include "phy_phase.h"
#include "iot_share_task.h"
#include "phy_dump.h"
#include "clk.h"
#include "phy_reg.h"
#if HW_PLATFORM >= HW_PLATFORM_FPGA
#include "phy_perf.h"
#include "mac_status.h"
#endif


void phy_fft_dump_recover()
{
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;

    /* tone disbale */
    phy_dfe_tone_cfg(0,0,0);

    /* disable force */
    phy_txrx_ovr_set(0,0);

    /* enable packet detect timeout */
    phy_pkt_time_out_disable(false);

    /* bypass dc blocker */
    tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
    REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 0);
    PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);

    /* fix gain and disable agc */
    phy_agc_gain_lvl_set(0,60,-24,0);

    /* enable adj and disable sat */
    phy_agc_sat_adj_set(0,0);

    /* disable auto-adjust gain */
    phy_agc_gain_adj_dis(0xE7FFC0FF);

    tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
    REG_FIELD_SET(SW_LOOPBACK_EN, tmp, 0);
    PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);

    /* config det tone */
    phy_update_tone_det_range();

#endif
}

int phy_rx_fft_done(int reg_addr)
{
    int ret = ERR_OK;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp;
    tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
    ret = REG_FIELD_GET(LOOP_FFT_DONE, tmp);
#endif
    (void)reg_addr;
    return ret;
}

uint32_t phy_rx_fft_dump( \
    uint32_t *buf_ptr, \
    int8_t gain, \
    uint8_t pkt_idx, \
    uint8_t pkt_max)
{
    uint32_t ret = ERR_OK;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;
    uint8_t timeout = 0;
    uint32_t core_freq = 0;
    uint32_t *csi_buf = (uint32_t *)BB_CSI_BASEADDR;

    /* check pkt idx and max valid */
    IOT_ASSERT(pkt_idx < pkt_max && pkt_max <= FFT_DUMP_PKT_MAX);

    /* first dump pkt */
    if(pkt_idx == 0) {
        /* save force value */
        tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
        g_phy_ctxt.dep.rx_phase_force_en = \
            REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL_FORCE_EN, tmp);
        g_phy_ctxt.dep.rx_phase_force = \
            REG_FIELD_GET(CFG_PHY_RX_PHASE_SEL, tmp);

        /* fix gain and disable agc */
        phy_agc_gain_lvl_set(1,gain,-24,0);

        /* enable rx all phase */
        phy_rx_phase_force_set_on_dump(true, PLC_PHASE_ALL);

        /* record core freq before fft trigger */
        core_freq = clk_core_freq_get();

        /* fft dump prepare */
        phy_fft_dump_prepare();

        /* wait fft done */
        timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
            CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
        if (timeout == ERR_TIMEOVER) {
            phy_force_0_access_require();
            /* check force rx abort */
            tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
            if (REG_FIELD_GET(CFG_PHY_RX_ABORT, tmp) != 0) {
                /* clr force */
                REG_FIELD_SET(CFG_PHY_RX_ABORT, tmp, 0);
                REG_FIELD_SET(CFG_PHY_RX_ABORT_FORCE_EN, tmp, 0);
                RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
                phy_force_0_access_release();

                /* try again */
                timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
                    CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
                if (timeout == ERR_TIMEOVER) {
                    IOT_ASSERT(0);
                }
            } else {
                phy_force_0_access_release();

                /* judge is rx status or not */
                extern uint32_t mac_get_phy_txrx_sts();
                /* MAC_PHY_RX_STS : 1 */
                if (mac_get_phy_txrx_sts() != 1) {
                    /* is not rx status, return */
                    return ERR_FAIL;
                }
                /* enable sw csi buf access */
                enable_sw_access_csi_buf(0);

                /* fft dump revert */
                phy_fft_dump_recover();

                /* fft dump prepare */
                phy_fft_dump_prepare();

                /* try again */
                timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
                    CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
                if (timeout == ERR_TIMEOVER) {
#if (IOT_FLASH_SIZE >=2 )
                    iot_printf("fft dump timeout FORCE_0:%x,"
                        "FORCE_1:%x,FORCE_2:%x,RD_MACPHY:%x\n", \
                        RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR), \
                        RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR), \
                        RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR), \
                        RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR));
#endif
                    uint32_t dbg_dump_buf[14] = {0};
                    dbg_dump_buf[0] = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
                    dbg_dump_buf[1] = RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR);
                    dbg_dump_buf[2] = RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR);
                    dbg_dump_buf[3] = RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR);
                    dbg_dump_buf[4] = PHY_RXTD_READ_REG(CFG_BB_AGC_DROP_TH_ADDR);
                    dbg_dump_buf[5] = PHY_RXTD_READ_REG(CFG_BB_AGC_RAMUP_TH_ADDR);
                    dbg_dump_buf[6] = core_freq;
                    dbg_dump_buf[7] = clk_core_freq_get();
                    dbg_dump_buf[8] = PHY_RXTD_READ_REG(CFG_RX_TD_DBG_BUS0_ADDR);
                    dbg_dump_buf[9] = PHY_RXTD_READ_REG(CFG_RX_TD_DBG_BUS1_ADDR);
                    dbg_dump_buf[10] = PHY_RXTD_READ_REG(CFG_RX_TD_DBG_BUS2_ADDR);
                    dbg_dump_buf[11] = PHY_RXTD_READ_REG(CFG_RX_TD_DBG_BUS3_ADDR);
                    dbg_dump_buf[12] = PHY_READ_REG(CFG_BB_TX_TD_DBG_BUS_ADDR);
                    dbg_dump_buf[13] = PHY_READ_REG(CFG_BB_TX_FD_FSM_DBG_BUS_ADDR);
                    mac_dump_buf(MAC_DUMP_TYPE_8, dbg_dump_buf, 14,
                        NULL, 0, NULL, 0, true);
                }
            }
        }

        /* enable sw csi buf access */
        enable_sw_access_csi_buf(1);
    }

    /* memcpy data from csi buf to buf */
    os_mem_cpy(buf_ptr, \
        csi_buf + pkt_idx * (IOT_PHY_CSI_BUF_LEN >> 2), \
        IOT_PHY_CSI_BUF_LEN);

    /* last dump pkt */
    if(pkt_idx == (pkt_max - 1)) {
        /* enable sw csi buf access */
        enable_sw_access_csi_buf(0);

        /* fft dump revert */
        phy_fft_dump_recover();

        /* recover force */
        phy_rx_phase_force_set_on_dump( \
            g_phy_ctxt.dep.rx_phase_force_en, \
            g_phy_ctxt.dep.rx_phase_force);
    }
#else
    (void)buf_ptr;
    (void)gain;
    (void)pkt_idx;
    (void)pkt_max;
#endif

    return ret;
}

uint32_t phy_rx_full_fft_dump(uint32_t *buf_ptr)
{
    uint32_t ret = ERR_OK;
#if HW_PLATFORM >= HW_PLATFORM_FPGA
    uint32_t tmp = 0;
    uint8_t timeout = 0;
    uint32_t *csi_buf = (uint32_t *)BB_CSI_BASEADDR;

    /* fft dump prepare */
    phy_fft_dump_prepare();

    /* wait fft done */
    timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
        CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
    if (timeout == ERR_TIMEOVER) {
        phy_force_0_access_require();
        /* check force rx abort */
        tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
        if (REG_FIELD_GET(CFG_PHY_RX_ABORT, tmp) != 0) {
            /* clr force */
            REG_FIELD_SET(CFG_PHY_RX_ABORT, tmp, 0);
            REG_FIELD_SET(CFG_PHY_RX_ABORT_FORCE_EN, tmp, 0);
            RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR, tmp);
            phy_force_0_access_release();

            /* try again */
            timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
                CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
            if (timeout == ERR_TIMEOVER) {
                IOT_ASSERT(0);
            }
        } else {
            phy_force_0_access_release();

            /* judge is rx status or not */
            extern uint32_t mac_get_phy_txrx_sts();
            /* MAC_PHY_RX_STS : 1 */
            if (mac_get_phy_txrx_sts() != 1) {
                /* is not rx status, return */
                return ERR_FAIL;
            }

            /* enable sw csi buf access */
            enable_sw_access_csi_buf(0);

            /* fft dump prepare */
            phy_fft_dump_prepare();

            /* try again */
            timeout = iot_wait_timeout_fun(phy_rx_fft_done, \
                CFG_BB_LOOPBACK_TEST_CFG_ADDR, 1, IOT_FFT_DONE_WAIT_MS);
            if (timeout == ERR_TIMEOVER) {
                IOT_ASSERT(0);
            }
        }
    }

    /* enable sw csi buf access */
    enable_sw_access_csi_buf(1);

    /* memcpy data from csi buf to buf */
    os_mem_cpy(buf_ptr, csi_buf, (TOTAL_TONE_MASK_NUM - 4) * 4);

    /* enable sw csi buf access */
    enable_sw_access_csi_buf(0);

#else
    (void)buf_ptr;
#endif

    return ret;
}