kunlun/tools/kl2_gdbinit

# These are some useful functions to add to your ~/.xt-gdbinit file
# Standard gdb debug settings

set history filename ~/.gdb_history
set history save on
set print pretty on
set print object on
set print vtbl on
set pagination off
set output-radix 16

set $new=1

define fpga_ver
x 0xa6048
end

define dmem_usage
end

define ana_read_gain
set *0x51c00180=1
x/w 0x51c0017c
set *0x51c00180=25
x/w 0x51c0017c
set *0x51c00180=41
x/w 0x51c0017c
end

define ana_read
set *0x51c00180=$arg0*4+1
x/w 0x51c0017c
x/b 0x51c00181
end

define ana_write
set $addr = $arg0
set $value = $arg1
set $mask = $arg2
set *0x51c00178=$mask
set *0x51c00174=$value
set *0x51c00180=$addr*4+3
end

define dump_all
set $phy_reg=0x51800000
set $phy_tx_reg=0x51900000
set $phy_rxtd_reg=0x51a00000
set $phy_rxfd_reg=0x51b00000
set $phy_dfe_reg=0x51c00000
set $mac_sys_reg=0x51000000
set $rgf_rx_reg=0x51000c00
set $ahb_reg=0x50000000
set $apb_reg=0x44000000
set $clk_reg=0x44009000
set $start=0
set $size=0x700/4
set $end=$size
set logging file phy_reg_dump.txt
set logging on
while $start < $end
    x $phy_reg+$start*4
    set $start++
end
set logging off

set logging file phy_tx_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $phy_tx_reg+$start*4
    set $start++
end
set logging off

set logging file phy_rxtd_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $phy_rxtd_reg+$start*4
    set $start++
end
set logging off

set logging file phy_rx_fd_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $phy_rxfd_reg+$start*4
    set $start++
end
set logging off

set logging file phy_dfe_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $phy_dfe_reg+$start*4
    set $start++
end
set logging off

set logging file mac_sys_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $mac_sys_reg+$start*4
    set $start++
end
set logging off

set logging file rgf_rx_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $rgf_rx_reg+$start*4
    set $start++
end
set logging off

set logging file ahb_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $ahb_reg+$start*4
    set $start++
end
set logging off

set logging file apb_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $apb_reg+$start*4
    set $start++
end
set logging off

set logging file clk_reg_dump.txt
set logging on
set $start=0
while $start < $end
    x $clk_reg+$start*4
    set $start++
end
set logging off

# reset fpga
define resetfpga
set *0x00100000=0x6f
set *0x50000004=0xffffffff
end

# Run to appstart and load app
define loadfw
monitor soft_reset_halt
disable_watchdog
load
set_cpu_freq_150
set $sp = &__StackTop
#set $pc = __Vectors[1]
end

#dump uart register
define dump_uart
p *(struct pl011_regs*)0x44001000
p *(struct pl011_regs*)0x44005000
end

define uart_info
p g_uart_info
end

#dump intc register
define dump_intc
p *(struct intc_regs*)0x44004000
end

#dump apb register
define dump_apb
p *(struct apb_regs*)0x44000000
end

#dump gptimer register
define dump_gptmr
p *(struct gpmtr_regs*)0x44003000
end

define cache_disable
set *0x50000008 &= ~(0x18)
set *0x50000004 |= (0x18)
# disable dmc cache
set *0x500000c8 = 0x000c0000
# disable icache1 cache
set *0x500000d8 = 0x000c0000
end

define map_flash_core
set *0x4400703c |= 0x30
set *0x44007098 |= 0x30
set *0x44007038 |= 0x30
set *0x44007064 |= 0x30
set *0x44007068 |= 0x30
set *0x44007040 |= 0x30

set *0x4400001c |= 0x4

set *0x44020010 |= 0x1000
set *0x44020014 |= 0x1000
set *0x44020018 |= 0x1000
set *0x4402001c |= 0x1000
end

define map_flash_gpio_ver14
# config pin 23-28 select FUNCTION0
set *0x44007080=0
set *0x44007084=0
set *0x44007088=0
set *0x4400708c=0
set *0x44007090=0
set *0x44007094=0
# enable gpio matrix
set *0x4400001c=0x4
# config gpio matrix in
# SFC INID 4-7 => GPIO 25-28
set *0x44020010=25
set *0x44020014=26
set *0x44020018=27
set *0x4402001c=28
#config gpio matrix out
# SFC OUTID 6-11 => GPIO 25-28
set *0x4402045c=0x6
set *0x44020460=0x7
set *0x44020464=0x8
set *0x44020468=0x9
set *0x4402046c=10
set *0x44020470=11
end

define map_uart2_gpio_mtx
set *0x44007040=0
set *0x44007044=0
set *0x4400001c=0x4
set *0x44020024=0x1000
set *0x4402002c=0x8
set *0x440200f8=15
end
define map_uart2_gpio_ver14
set *0x44007040=0
set *0x44007044=0
set *0x4400001c |= 0x4
set *0x44020024 |= 0x1000
set *0x4402002c=0x8
set *0x44020464=15
end

define map_psram_core_def
set *0x4400001c |= 0x4
set *0x44020000 |= 0x1000
set *0x44020004 |= 0x1000
set *0x44020008 |= 0x1000
set *0x4402000c |= 0x1000
end

define set_cache_buffer_mode
set *0x5000000c=0x10000
set *0x50000008=0x00090010
set *0x50000004=0xe
end

define cache_qspi_enable
set *0x50000004=0x2001A
set *0x50000008=0x90004
# modify
set *0x52000188=0x03057a75
set *0x5200018c=0x100
set *0x52000190=0x08180000
# dual
#set *0x52000188=0x3b057a75
#set *0x5200018c=0x102
#set *0x52000190=0x08180008
#quad
#set *0x52000188=0xeb057a75
#set *0x5200018c=0x115
#set *0x52000190=0x08060204

set *0x52000194=0x100
set *0x52000198=0x08000000
set *0x5200019c=0x100
set *0x520001a0=0x08000000
set *0x520001a4=0x100
set *0x520001a8=0x08000000
#set *0x52000130=0x3
# set cache quad
#set *0x5200020c=0x102
set *0x5200020c=0x1102
set *0x52000208=0x35000000
set *0x52000204=0x80000000

set *0x50000004=0x20002
set *0x50000008=0x9001C
end

define enable_emc
set *0x62000004 |= 0x1
set *0x62000008 |= 0x1
set *0x62000008 &= ~(0x1)
end

define init_flash
set *0x61000140=0x2000
#set *0x61000188=0x03057a75
#set *0x6100018c=0x100
#set *0x61000190=0x08180000
set *0x52000188=0xeb057a75
set *0x5200018c=0x115
set *0x52000190=0x08060204

set *0x61000194=0x100
set *0x61000198=0x08000000
set *0x6100019c=0x100
set *0x610001a0=0x08000000
set *0x610001a4=0x100
set *0x610001a8=0x08000000
end

define psram_qpi_mode
set *0x6100020c=0x1102
set *0x61000208=0x35000000
set *0x61000204=0x80000000
end

define psram_spi_mode
set *0x6100020c=0x1000
set *0x61000208=0xf5000000
set *0x61000204=0x80000000
set *0x6100020c=0x0000
end

define space_cache
set $val = $arg0
set *0x5000008c = $val
end

define enable_cache
set *0x50000008 |= 0x18
set *0x50000004 &= ~(0x18)
# dmc cache enable
set *0x500000c8 |= 0x20000
set *0x500000c8 &= ~0x140000
# dmc cache enable
set *0x500000d8 |= 0x20000
set *0x500000d8 &= ~0x40000
end

define cache_cfg_qpi_ver14
enable_emc
#init_flash
psram_qpi_mode
enable_cache
space_cache 0x44
end

define cache_cfg_spi_ver14
enable_emc
psram_spi_mode
init_flash
enable_cache
space_cache 0x44
end

define loadfirmware
monitor soft_reset_halt
cache_disable
map_flash_gpio_mtx
map_psram_core_def
map_uart2_gpio_mtx
cache_qspi_enable
load
end

define disable_watchdog
set *0x44000004 |= 0x2000
set *0x62000004 |= 0x10
set *0x4400001c |= 0x1000
set *0x90008000 |= 0x40000040
set *0x4400e080 = 0x57444750
set *0x4400e008 = 0
set *0x62010080 = 0x57444750
set *0x62010008 = 0
set *0x4402a080 = 0x57444750
set *0x4402a008 = 0
set *0x90005080 = 0x57444750
set *0x90005008 = 0
set *0x90010080 = 0x57444750
set *0x90010008 = 0
set *0x4400e080 = 0
set *0x62010080 = 0
set *0x4402a080 = 0
set *0x90005080 = 0
set *0x90010080 = 0
end

define set_cpu_freq_150
set *0x44009004=0x100
set *0x44009000=0x1
end

define set_sfc_clk_75
set *0x61000134=0x10
end

define set_smc_clk_75
set *0x61000210=0x10
end

define load_ver14_qpi
monitor soft_reset_halt
disable_watchdog
cache_disable
if $new == 1
    map_flash_core
else
    map_flash_gpio_ver14
end
map_psram_core_def
#map_uart2_gpio_ver14
cache_cfg_qpi_ver14
load
set_cpu_freq_150
#set_sfc_clk_75
#set_smc_clk_75
while $a0 != 0x0
    set $a0=0x0
end
end

define load_ver14_spi
monitor soft_reset_halt
disable_watchdog
cache_disable
if $new == 1
    map_flash_core
else
    map_flash_gpio_ver14
end
map_psram_core_def
#map_uart2_gpio_ver14
cache_cfg_spi_ver14
load
set $a0=0x0
end

define snapshot
set *0x52000004=0x10101
set *0x52000008=0x1e007
end

define map_jtag_gpio_mtx
# config pin 00 - 04 select FUCNTION0
set *0x44007024=0
set *0x44007028=0
set *0x4400702c=0
set *0x44007030=0
set *0x44007034=0
# enable gpio matrix
set *0x4400001c=0x4
#in 44 - 47 => 00 01 03 04
set *0x440200b0=00
set *0x440200b4=01
set *0x440200b8=03
set *0x440200bc=04
#out 2 => 66
set *0x44020408=62
end

define map_jtag0_gpio
#config pin 12-15 45 select FUNCTION0
set *0x44007054 = 0
set *0x44007058 = 0
set *0x4400705c = 0
set *0x44007060 = 0
set *0x440070a0 = 0
# enable gpio matrix
set *0x4400001c=0x4
#in 44 TMS 12
set *0x440200b0=12
#in 45 TCK 13
set *0x440200b4=13
#in 46 TDI 15
set *0x440200b8=15
#in 47 RST 45
set *0x440200bc=45
#out 14 => 62
set *0x44020438=62
end

define print_dump_info
    set trace-commands off
    set $i = 0
    while($i < 10)
        set $dump = g_exception_dump.ra[$i]
        if ($dump != 0x0)
            p/a $dump
        end
        set $i = $i + 1
    end
    set trace-commands on
end

define map_dmc_psram
    set *0x5522a03c = 0x15501
end

define map_emc_flash_kl2
# 48 - 53
set *0x440070c4 &= ~0x30
set *0x440070c8 &= ~0x30
set *0x440070cc &= ~0x30
set *0x440070d0 &= ~0x30
set *0x440070d4 &= ~0x30
set *0x440070d8 &= ~0x30
set *0x440070c4 |= 0x10
set *0x440070c8 |= 0x10
set *0x440070cc |= 0x10
set *0x440070d0 |= 0x10
set *0x440070d4 |= 0x10
set *0x440070d8 |= 0x10
set *0x440070dc |= 0x10

set *0x4400001c |= 0x4

set *0x44020010 |= 0x1000
set *0x44020014 |= 0x1000
set *0x44020018 |= 0x1000
set *0x4402001c |= 0x1000
end

# reg_write reg lowest_bit bit_num value
define reg_write
    set $reg = $arg0
    set $low = $arg1
    set $cnt = $arg2
    set $value = $arg3
    set $tmp = *(uint32_t *)$reg
    set $mask = 0
    while($cnt > 0)
        set $cnt--
        set $mask = (($mask << 1) + 1)
    end
    set $mask = $mask << $low
    set $tmp &= ~$mask
    set $tmp |= (($value << $low) & $mask)
    set *(uint32_t *)$reg = $tmp
end

define ddr_op_clear
    reg_write 0x5522811c 8 1 0
    reg_write 0x5522811c 0 2 0
    reg_write 0x5522801c 8 1 0
    reg_write 0x55228004 6 2 3
    reg_write 0x55228004 6 2 0
end

define ddr_soft_read
    set trace-commands off
    set $instr = $arg0
    set $addr = $arg1
    # step 1
    reg_write 0x5522811c 9 1 0
    reg_write 0x5522811c 0 2 0
    reg_write 0x55228004 6 2 3
    reg_write 0x55228004 6 2 0
    echo step1 finish\n

    #step 2
    reg_write 0x5522801c 8 1 0
    reg_write 0x5522801c 0 8 $instr
    reg_write 0x55228020 0 32 $addr
    reg_write 0x5522811c 8 1 0
    reg_write 0x5522801c 8 1 1
    echo step2 finish\n

    # step 3
    reg_write 0x5522811c 8 1 1
    reg_write 0x5522811c 1 1 1
    reg_write 0x5522811c 0 1 1
    echo step3 finish\n

    #step 4
    echo \nrdata0:\n
    x/x 0x55228108
    echo \nrdata1:\n
    x/x 0x55228120

    # reset clear
    ddr_op_clear
    set trace-commands on
end

define ddr_soft_write
    set trace-commands off
    set $instr = $arg0
    set $addr = $arg1
    set $latency = $arg2
    set $wdata0 = $arg3
    set $wdata1 = $arg4
    # step 1
    reg_write 0x5522811c 9 1 1
    reg_write 0x5522811c 0 2 0
    reg_write 0x55228004 6 2 3
    reg_write 0x55228004 6 2 0
    reg_write 0x55228010 16 4 $latency
    echo step1 finish\n

    # step 2
    reg_write 0x5522801c 8 1 0
    reg_write 0x5522801c 0 8 $instr
    reg_write 0x55228020 0 32 $addr
    reg_write 0x5522811c 8 1 0
    reg_write 0x5522801c 8 1 1
    echo step2 finish\n

    # step 3
    reg_write 0x5522811c 8 1 1
    reg_write 0x55228100 0 32 $wdata0
    reg_write 0x55228104 28 1 0
    if ($instr == 0xc0)
        reg_write 0x55228104 0 24 0x6db69a
    else
        reg_write 0x55228104 0 24 0x69a69a
    end
    reg_write 0x5522811c 3 1 1
    reg_write 0x5522811c 8 1 1
    reg_write 0x55228100 0 32 $wdata1
    reg_write 0x55228104 28 1 0
    if ($instr == 0xc0)
        reg_write 0x55228104 0 24 0x6db6db
    else
        reg_write 0x55228104 0 24 0x69a69a
    end
    reg_write 0x5522811c 3 1 1
    echo step3 finish\n

    # step 4
    reg_write 0x55228100 0 32 0
    reg_write 0x55228104 28 1 0
    reg_write 0x55228104 0 24 0xaebaeb
    reg_write 0x5522811c 3 1 1
    reg_write 0x5522811c 3 1 1
    reg_write 0x5522811c 1 1 1
    echo step4 finish\n

    # reset clear
    ddr_op_clear
    set trace-commands on
end

define ddr_mode_x8
    reg_write 0x55228008 1 2 2
    reg_write 0x55228008 4 4 6
    reg_write 0x55228014 0 4 6
end

define ddr_mode_x16
    reg_write 0x55228008 1 2 1
    reg_write 0x55228014 0 4 5
end

define ddr_cfg
    # set ddr mode
    ddr_mode_x16
    # set ddr reg0 to 0x01
    #ddr_soft_write 0xc0 0 1 0x01010101 0x01010101
    # set ddr reg4 to 0x0
    #ddr_soft_write 0xc0 4 1 0x0 0x0
    # set ddr read/write latency
    #reg_write 0x55228010 16 8 0x33
    # set ddr echo chip size, size = 2^n Mb, now 16MB
    reg_write 0x55228008 4 4 7
    # set dmc echo chip size, size = 2^n Mb, now 16MB
    reg_write 0x5522a008 8 4 7

    #ddr_op_clear
end

define ddr_cfg_x8
    # set ddr mode
    ddr_mode_x8
    # set dmc echo chip size, size = 2^n Mb, now 8MB
    reg_write 0x5522a008 8 4 6
end

define ddr_dmc_mode
set *0x5000000c |= 0x180000
set *0x500000d8 |= 0x100000
end

define load_kl2_psram
#monitor soft_reset_halt
cache_disable
map_dmc_psram
map_emc_flash_kl2
cache_cfg_qpi_ver14
space_cache 0x1004
load
while $a0 != 0x0
    set $a0=0x0
end
end

define load_kl2_ddr
#monitor soft_reset_halt
cache_disable
ddr_cfg
map_emc_flash_kl2
enable_cache
space_cache 0x1004
ddr_dmc_mode
load
while $a0 != 0x0
    set $a0=0x0
end
end

define load_kl2_ddr_x8
#monitor soft_reset_halt
cache_disable
ddr_cfg_x8
map_emc_flash_kl2
enable_cache
space_cache 0x0804
ddr_dmc_mode
load
while $a0 != 0x0
    set $a0=0x0
end
end

define load_kl2_a10
#monitor soft_reset_halt
cache_disable
ddr_cfg
enable_cache
space_cache 0x4008
ddr_dmc_mode
load
while $a0 != 0x0
    set $a0=0x0
end
end

define load_kl2_a10_x8
#monitor soft_reset_halt
cache_disable
ddr_cfg_x8
enable_cache
space_cache 0x4008
ddr_dmc_mode
load
while $a0 != 0x0
    set $a0=0x0
end
end

define k3d_enable
#ahb ai enable
set *0x50000008 |= 0x80
set *0x50000004 |= 0x80
set *0x50000004 &= ~0x80
#ai k3d ena
set *0x70000000 |= 0x1

#ahb dvp enable
set *0x50000008 |= 0x800
set *0x50000004 |= 0x800
set *0x50000004 &= ~0x800
end

define k3d_disable
set *0x70000000 &= ~0x1
end

define dvp_enable
set *0x50000008 |= 0x800
set *0x50000004 |= 0x800
set *0x50000004 &= ~0x800
end

define dvp_ram_mode
set *0x52300000 = 0x21f21
set *0x52300054 = 0x3
set *0x52300004 = 0x1cc
set *0x52300008 = 0x1
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
set *0x52300100 = 0x1
end

define dvp_ram_mode_no_force
set *0x52300000 = 0x0
set *0x52300054 = 0x3
set *0x52300004 = 0x1cc
set *0x52300008 = 0x1
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
set *0x52300100 = 0x1
set *0x52300000 = 0x01f01
end

define dvp_ram_mode_crop
# dvp data to psram address
set *0x52300018 = 0x00000
set *0x5230010c = 0x100000
set *0x52300000 = 0x0
set *0x52300054 = 0x0
set *0x52300004 = 0x11cc

#set *0x52300008 = 0x1
#set *0x5230000c = 0xff
#set *0x52300010 = 0x02cf04ff
set *0x52300008 = 0x1
set *0x5230000c = 0x1
set *0x52300010 = 0x02cf0400

set *0x52300014 = 0x04000000
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300000 = 0x01f33
end

define dvp_ram_mode_no_crop
# dvp data to psram address
set *0x52300018 = 0x00000
set *0x5230010c = 0x1000000
set *0x52300000 = 0x0
set *0x52300054 = 0x0
set *0x52300004 = 0x11cc
set *0x52300008 = 0x1
set *0x5230000c = 0x1
set *0x52300010 = 0x02cf0400
set *0x52300014 = 0x05000000
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300000 = 0x01f31
end

define dvp_bina_mode
set *0x52300000 = 0x021f21
set *0x52300054 = 0x5
set *0x52300004 = 0x1cc
set *0x52300008 = 0x1
#set *0x52300024 = 720
#set *0x52300028 = 1280
set *0x52300024 = 720
set *0x52300028 = 1024
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
end

define dvp_bina_mode_no_force
set *0x52300000 = 0x0
set *0x52300054 = 0x5
set *0x52300004 = 0x1cc
set *0x52300008 = 0x1
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
set *0x52300000 = 0x001f21
end

define dvp_bina_mode_auto
set *0x52300000 = 0x0
set *0x52300054 = 0x7
set *0x52300004 = 0x11cc
set *0x52300008 = 0x1
set *0x52300024 = 720
set *0x52300028 = 1280
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
set *0x52300000 = 0x001f21
end
# crop 1024 * 720
define dvp_bina_mode_crop
set *0x52300000 = 0x0
# dvp data to psram address
set *0x52300018 = 0x10000
set *0x52300054 = 0x7
set *0x52300004 = 0x11cc
set *0x52300008 = 0x1
set *0x5230000c = 0xff
#set *0x5230000c = 0x0
set *0x52300010 = 0x02d004ff
#set *0x52300010 = 0x02d00400
set *0x52300024 = 720
#set *0x52300028 = 1280
set *0x52300028 = 1024
set *0x52300060 = 0x1
set *0x52300058 = 0x72105
set *0x523000b4 = 0x72ff
set *0x52300000 = 0x001f23
end

define fake_data
set $addr = $arg0
set $size = $arg1
set $offset = $arg2
set $i = 0
while $size > 0
    set *$addr =  $i
    set $i = $i + 0x11111111 + $offset
    if ($i == 0xffffffff)
        set $i = 0x0
    end
    set $addr = $addr + 4
    set $size = $size - 1
end
end

define ai_glb_config
reg_write 0x7000000c 0 20 0x38400
reg_write 0x70000010 0 16 0x5760
reg_write 0x70000014 0 17 0x0
reg_write 0x70000018 0 17 0x1680
reg_write 0x7000001c 0 32 0
set *0x70000008 = 0x4005
set *0x70000000 = 0x4531
end

define clear_cache
set *0x5000000c |= 0xc
end

define cpu0_enable
set $start_pc = $arg0
set *0x5000004c = $start_pc
set *0x50000008 |= 0x10000
set *0x50000004 |= 0x10000
set *0x50000004 &= ~0x10000
end

define cpu2_enable
set $start_pc = $arg0
set *0x500000b0 = $start_pc
set *0x50000008 |= 0x20000
set *0x50000004 |= 0x20000
set *0x50000004 &= ~0x20000
end

define vm
target remote localhost:3333
disable_watchdog
end

define kl2_vm
vm
monitor reset halt
kill
shell sleep 0.001
vm
end

define kl2_target_remote

target remote $arg0
monitor reset halt
kill
shell sleep 0.001
target remote $arg0
disable_watchdog
end

define bpll_calibration
reg_write 0x90008074 13 2 0
reg_write 0x90008074 6 1 1
reg_write 0x900080f8 12 1 1
reg_write 0x900080f8 12 1 0
reg_write 0x90008078 0 7 100
reg_write 0x90008074 6 1 0
reg_write 0x90008074 6 1 0
reg_write 0x90008074 13 1 1
set $done = 1
while($done == 1)
    set $i = *(uint32_t *) 0x90008078
    set $i = $i & 0x20000
    if $i > 0
        set $done = 0
    end
end
end

define set_level_to_1p1
set *0x90008000 = 0x80
reg_write 0x9000f034 24 1 0
reg_write 0x9000f034 26 4 9
end

define switch_to_150m
set_level_to_1p1
# enable ana_reg
set *0x44000004 |= 0x40000
reg_write 0x4401101c 17 8 36
bpll_calibration
set *0x44009000 = 0x4165
end

define set_level_to_1p2
set *0x90008000 = 0x80
reg_write 0x9000f034 24 1 0
reg_write 0x9000f034 26 4 14
end

define switch_to_200m
set_level_to_1p2
# enable ana_reg
set *0x44000004 |= 0x40000
reg_write 0x4401101c 17 8 48
bpll_calibration
set *0x44009000 = 0x4165
end