kunlun/inc/hw/reg/riscv2/15/apb_glb_reg.h

//-----------------------------------
#define CFG_APB_RVER_ADDR 0x0000
#define APB_RF_VER_OFFSET 0
#define APB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_APB_GLB_GEN0_ADDR 0x0004
#define MCLK_AUDIO_EB_OFFSET 31
#define MCLK_AUDIO_EB_MASK 0x80000000
#define IIS4_EB_OFFSET 30
#define IIS4_EB_MASK 0x40000000
#define SADC_EB_OFFSET 29
#define SADC_EB_MASK 0x20000000
#define IIS3_EB_OFFSET 28
#define IIS3_EB_MASK 0x10000000
#define PWM5_EB_OFFSET 27
#define PWM5_EB_MASK 0x08000000
#define PWM4_EB_OFFSET 26
#define PWM4_EB_MASK 0x04000000
#define PWM3_EB_OFFSET 25
#define PWM3_EB_MASK 0x02000000
#define PWM2_EB_OFFSET 24
#define PWM2_EB_MASK 0x01000000
#define PWM1_EB_OFFSET 23
#define PWM1_EB_MASK 0x00800000
#define PWM0_EB_OFFSET 22
#define PWM0_EB_MASK 0x00400000
#define IIS2_EB_OFFSET 21
#define IIS2_EB_MASK 0x00200000
#define IIS1_EB_OFFSET 20
#define IIS1_EB_MASK 0x00100000
#define IIS0_EB_OFFSET 19
#define IIS0_EB_MASK 0x00080000
#define ANA_REG_EB_OFFSET 18
#define ANA_REG_EB_MASK 0x00040000
#define DMA_HW_EB_OFFSET 17
#define DMA_HW_EB_MASK 0x00020000
#define UART_MEM_EB_OFFSET 16
#define UART_MEM_EB_MASK 0x00010000
#define UART_3_EB_OFFSET 15
#define UART_3_EB_MASK 0x00008000
#define CAN1_EB_OFFSET 14
#define CAN1_EB_MASK 0x00004000
#define WDG0_EB_OFFSET 13
#define WDG0_EB_MASK 0x00002000
#define SPI_S0_EB_OFFSET 11
#define SPI_S0_EB_MASK 0x00000800
#define SPI_M1_EB_OFFSET 10
#define SPI_M1_EB_MASK 0x00000400
#define SPI_M0_EB_OFFSET 9
#define SPI_M0_EB_MASK 0x00000200
#define CLKREG_EB_OFFSET 8
#define CLKREG_EB_MASK 0x00000100
#define CAN0_EB_OFFSET 7
#define CAN0_EB_MASK 0x00000080
#define PINREG_EB_OFFSET 6
#define PINREG_EB_MASK 0x00000040
#define UART_2_EB_OFFSET 5
#define UART_2_EB_MASK 0x00000020
#define UART_1_EB_OFFSET 4
#define UART_1_EB_MASK 0x00000010
#define INTC0_EB_OFFSET 3
#define INTC0_EB_MASK 0x00000008
#define GTMR0_EB_OFFSET 2
#define GTMR0_EB_MASK 0x00000004
#define GPIO_EB_OFFSET 1
#define GPIO_EB_MASK 0x00000002
#define UART_0_EB_OFFSET 0
#define UART_0_EB_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST0_ADDR 0x0008
#define IIS4_SOFT_RST_OFFSET 30
#define IIS4_SOFT_RST_MASK 0x40000000
#define SADC_SOFT_RST_OFFSET 29
#define SADC_SOFT_RST_MASK 0x20000000
#define IIS3_SOFT_RST_OFFSET 28
#define IIS3_SOFT_RST_MASK 0x10000000
#define PWM5_SOFT_RST_OFFSET 27
#define PWM5_SOFT_RST_MASK 0x08000000
#define PWM4_SOFT_RST_OFFSET 26
#define PWM4_SOFT_RST_MASK 0x04000000
#define PWM3_SOFT_RST_OFFSET 25
#define PWM3_SOFT_RST_MASK 0x02000000
#define PWM2_SOFT_RST_OFFSET 24
#define PWM2_SOFT_RST_MASK 0x01000000
#define PWM1_SOFT_RST_OFFSET 23
#define PWM1_SOFT_RST_MASK 0x00800000
#define PWM0_SOFT_RST_OFFSET 22
#define PWM0_SOFT_RST_MASK 0x00400000
#define IIS2_SOFT_RST_OFFSET 21
#define IIS2_SOFT_RST_MASK 0x00200000
#define IIS1_SOFT_RST_OFFSET 20
#define IIS1_SOFT_RST_MASK 0x00100000
#define IIS0_SOFT_RST_OFFSET 19
#define IIS0_SOFT_RST_MASK 0x00080000
#define ANA_REG_SOFT_RST_OFFSET 18
#define ANA_REG_SOFT_RST_MASK 0x00040000
#define DMA_HW_SOFT_RST_OFFSET 17
#define DMA_HW_SOFT_RST_MASK 0x00020000
#define UART_MEM_SOFT_RST_OFFSET 16
#define UART_MEM_SOFT_RST_MASK 0x00010000
#define UART_3_SOFT_RST_OFFSET 15
#define UART_3_SOFT_RST_MASK 0x00008000
#define CAN1_SOFT_RST_OFFSET 14
#define CAN1_SOFT_RST_MASK 0x00004000
#define WDG0_SOFT_RST_OFFSET 13
#define WDG0_SOFT_RST_MASK 0x00002000
#define SPI_S0_SOFT_RST_OFFSET 11
#define SPI_S0_SOFT_RST_MASK 0x00000800
#define SPI_M1_SOFT_RST_OFFSET 10
#define SPI_M1_SOFT_RST_MASK 0x00000400
#define SPI_M0_SOFT_RST_OFFSET 9
#define SPI_M0_SOFT_RST_MASK 0x00000200
#define CLKREG_SOFT_RST_OFFSET 8
#define CLKREG_SOFT_RST_MASK 0x00000100
#define CAN0_SOFT_RST_OFFSET 7
#define CAN0_SOFT_RST_MASK 0x00000080
#define PINREG_SOFT_RST_OFFSET 6
#define PINREG_SOFT_RST_MASK 0x00000040
#define UART_2_SOFT_RST_OFFSET 5
#define UART_2_SOFT_RST_MASK 0x00000020
#define UART_1_SOFT_RST_OFFSET 4
#define UART_1_SOFT_RST_MASK 0x00000010
#define INTC0_SOFT_RST_OFFSET 3
#define INTC0_SOFT_RST_MASK 0x00000008
#define GTMR0_SOFT_RST_OFFSET 2
#define GTMR0_SOFT_RST_MASK 0x00000004
#define GPIO_SOFT_RST_OFFSET 1
#define GPIO_SOFT_RST_MASK 0x00000002
#define UART_0_SOFT_RST_OFFSET 0
#define UART_0_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GPIO_CFG_ADDR 0x000c
#define GPIO_ENA_CFG_OFFSET 0
#define GPIO_ENA_CFG_MASK 0x000001FF

//-----------------------------------
#define CFG_APB_GLB_CTRL_ADDR 0x0010
#define GLB_CTRL0_OFFSET 0
#define GLB_CTRL0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_APB_UART_LR_ADDR 0x0014
#define PUART3_FIFO_LR_OFFSET 3
#define PUART3_FIFO_LR_MASK 0x00000008
#define PUART2_FIFO_LR_OFFSET 2
#define PUART2_FIFO_LR_MASK 0x00000004
#define PUART1_FIFO_LR_OFFSET 1
#define PUART1_FIFO_LR_MASK 0x00000002
#define PUART0_FIFO_LR_OFFSET 0
#define PUART0_FIFO_LR_MASK 0x00000001

//-----------------------------------
#define CFG_APB_REG_PROT_ADDR 0x0018
#define APB_GLB_GRST1_UNLOCK_OFFSET 3
#define APB_GLB_GRST1_UNLOCK_MASK 0x00000008
#define APB_GLB_GRST0_UNLOCK_OFFSET 2
#define APB_GLB_GRST0_UNLOCK_MASK 0x00000004
#define APB_GLB_GEN1_UNLOCK_OFFSET 1
#define APB_GLB_GEN1_UNLOCK_MASK 0x00000002
#define APB_GLB_GEN0_UNLOCK_OFFSET 0
#define APB_GLB_GEN0_UNLOCK_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GEN1_ADDR 0x001c
#define FMST_EB_OFFSET 17
#define FMST_EB_MASK 0x00020000
#define AUDIO_WK_EB_OFFSET 16
#define AUDIO_WK_EB_MASK 0x00010000
#define SPINLOCK_EB_OFFSET 15
#define SPINLOCK_EB_MASK 0x00008000
#define GTMR2_EB_OFFSET 14
#define GTMR2_EB_MASK 0x00004000
#define INTC2_EB_OFFSET 13
#define INTC2_EB_MASK 0x00002000
#define WDG2_EB_OFFSET 12
#define WDG2_EB_MASK 0x00001000
#define I2C0_S_EB_OFFSET 11
#define I2C0_S_EB_MASK 0x00000800
#define I2C2_EB_OFFSET 10
#define I2C2_EB_MASK 0x00000400
#define LEDC_EB_OFFSET 9
#define LEDC_EB_MASK 0x00000200
#define I2C1_EB_OFFSET 8
#define I2C1_EB_MASK 0x00000100
#define I2C0_EB_OFFSET 7
#define I2C0_EB_MASK 0x00000080
#define SIG_PWM3_EB_OFFSET 6
#define SIG_PWM3_EB_MASK 0x00000040
#define SIG_PWM2_EB_OFFSET 5
#define SIG_PWM2_EB_MASK 0x00000020
#define SIG_PWM1_EB_OFFSET 4
#define SIG_PWM1_EB_MASK 0x00000010
#define SIG_PWM0_EB_OFFSET 3
#define SIG_PWM0_EB_MASK 0x00000008
#define GMTX_EB_OFFSET 2
#define GMTX_EB_MASK 0x00000004

//-----------------------------------
#define CFG_APB_GLB_GRST1_ADDR 0x0020
#define FMST_SOFT_RST_OFFSET 17
#define FMST_SOFT_RST_MASK 0x00020000
#define AUDIO_WK_SOFT_RST_OFFSET 16
#define AUDIO_WK_SOFT_RST_MASK 0x00010000
#define SPINLOCK_SOFT_RST_OFFSET 15
#define SPINLOCK_SOFT_RST_MASK 0x00008000
#define GTMR2_SOFT_RST_OFFSET 14
#define GTMR2_SOFT_RST_MASK 0x00004000
#define WDG2_SOFT_RST_OFFSET 13
#define WDG2_SOFT_RST_MASK 0x00002000
#define INTC2_SOFT_RST_OFFSET 12
#define INTC2_SOFT_RST_MASK 0x00001000
#define I2C0_S_SOFT_RST_OFFSET 11
#define I2C0_S_SOFT_RST_MASK 0x00000800
#define I2C2_SOFT_RST_OFFSET 10
#define I2C2_SOFT_RST_MASK 0x00000400
#define LEDC_SOFT_RST_OFFSET 9
#define LEDC_SOFT_RST_MASK 0x00000200
#define I2C1_SOFT_RST_OFFSET 8
#define I2C1_SOFT_RST_MASK 0x00000100
#define I2C0_SOFT_RST_OFFSET 7
#define I2C0_SOFT_RST_MASK 0x00000080
#define SIG_PWM3_SOFT_RST_OFFSET 6
#define SIG_PWM3_SOFT_RST_MASK 0x00000040
#define SIG_PWM2_SOFT_RST_OFFSET 5
#define SIG_PWM2_SOFT_RST_MASK 0x00000020
#define SIG_PWM1_SOFT_RST_OFFSET 4
#define SIG_PWM1_SOFT_RST_MASK 0x00000010
#define SIG_PWM0_SOFT_RST_OFFSET 3
#define SIG_PWM0_SOFT_RST_MASK 0x00000008
#define GMTX_SOFT_RST_OFFSET 2
#define GMTX_SOFT_RST_MASK 0x00000004

//-----------------------------------
#define CFG_APB_UART_CFG_ADDR 0x0024
#define UART3_DMA_HW_EB_OFFSET 19
#define UART3_DMA_HW_EB_MASK 0x00080000
#define UART2_DMA_HW_EB_OFFSET 18
#define UART2_DMA_HW_EB_MASK 0x00040000
#define UART1_DMA_HW_EB_OFFSET 17
#define UART1_DMA_HW_EB_MASK 0x00020000
#define UART0_DMA_HW_EB_OFFSET 16
#define UART0_DMA_HW_EB_MASK 0x00010000
#define UART3_RXD_FROM_ANA_OFFSET 11
#define UART3_RXD_FROM_ANA_MASK 0x00000800
#define UART2_RXD_FROM_ANA_OFFSET 10
#define UART2_RXD_FROM_ANA_MASK 0x00000400
#define UART1_RXD_FROM_ANA_OFFSET 9
#define UART1_RXD_FROM_ANA_MASK 0x00000200
#define UART0_RXD_FROM_ANA_OFFSET 8
#define UART0_RXD_FROM_ANA_MASK 0x00000100
#define CLK_38KHZ_ENA_OFFSET 4
#define CLK_38KHZ_ENA_MASK 0x00000010
#define UART3_IRDA_MODE_OFFSET 3
#define UART3_IRDA_MODE_MASK 0x00000008
#define UART2_IRDA_MODE_OFFSET 2
#define UART2_IRDA_MODE_MASK 0x00000004
#define UART1_IRDA_MODE_OFFSET 1
#define UART1_IRDA_MODE_MASK 0x00000002
#define UART0_IRDA_MODE_OFFSET 0
#define UART0_IRDA_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_ANA_MPTX_CFG0_ADDR 0x0028

//-----------------------------------
#define CFG_ANA_MPTX_CFG1_ADDR 0x002C

//-----------------------------------
#define CFG_SIG_PWM0_CFG_ADDR 0x0030
#define SIG_PWM0_PRESCALAR_OFFSET 8
#define SIG_PWM0_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM0_TARGET_OFFSET 0
#define SIG_PWM0_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM1_CFG_ADDR 0x0034
#define SIG_PWM1_PRESCALAR_OFFSET 8
#define SIG_PWM1_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM1_TARGET_OFFSET 0
#define SIG_PWM1_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM2_CFG_ADDR 0x0038
#define SIG_PWM2_PRESCALAR_OFFSET 8
#define SIG_PWM2_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM2_TARGET_OFFSET 0
#define SIG_PWM2_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG_PWM3_CFG_ADDR 0x003c
#define SIG_PWM3_PRESCALAR_OFFSET 8
#define SIG_PWM3_PRESCALAR_MASK 0x0000FF00
#define SIG_PWM3_TARGET_OFFSET 0
#define SIG_PWM3_TARGET_MASK 0x000000FF

//-----------------------------------
#define CFG_APB_SADC_CFG2_ADDR 0x0040
#define SADC_SEL_FAST_OFFSET 0
#define SADC_SEL_FAST_MASK 0x00000001

//-----------------------------------
#define CFG_FTST_CFG_ADDR 0x0044
#define SEC_DMA_FORCE_ON_OFFSET 11
#define SEC_DMA_FORCE_ON_MASK 0x00000800
#define FDMA_AHB_FSM_OFFSET 8
#define FDMA_AHB_FSM_MASK 0x00000700
#define FDMA_IO_MODE_OFFSET 4
#define FDMA_IO_MODE_MASK 0x00000070
#define FUNCTST_FORCE_EB_OFFSET 0
#define FUNCTST_FORCE_EB_MASK 0x00000001

//-----------------------------------
#define CFG_EFUSE_CFG0_ADDR 0x0050
#define EFUSE_RDATA0_OFFSET 0
#define EFUSE_RDATA0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG1_ADDR 0x0054
#define EFUSE_RDATA1_OFFSET 0
#define EFUSE_RDATA1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG2_ADDR 0x0058
#define EFUSE_RDATA2_OFFSET 0
#define EFUSE_RDATA2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG3_ADDR 0x005c
#define EFUSE_RDATA3_OFFSET 0
#define EFUSE_RDATA3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG4_ADDR 0x0060
#define EFUSE_RDATA4_OFFSET 0
#define EFUSE_RDATA4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG5_ADDR 0x0064
#define EFUSE_RDATA5_OFFSET 0
#define EFUSE_RDATA5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG6_ADDR 0x0068
#define EFUSE_RDATA6_OFFSET 0
#define EFUSE_RDATA6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG7_ADDR 0x006c
#define EFUSE_RDATA7_OFFSET 0
#define EFUSE_RDATA7_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG8_ADDR 0x0070
#define EFUSE_RDATA8_OFFSET 0
#define EFUSE_RDATA8_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG9_ADDR 0x0074
#define EFUSE_RDATA9_OFFSET 0
#define EFUSE_RDATA9_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG10_ADDR 0x0078
#define EFUSE_RDATA10_OFFSET 0
#define EFUSE_RDATA10_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG11_ADDR 0x007c
#define EFUSE_RDATA11_OFFSET 0
#define EFUSE_RDATA11_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG12_ADDR 0x0080
#define EFUSE_RDATA12_OFFSET 0
#define EFUSE_RDATA12_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG13_ADDR 0x0084
#define EFUSE_RDATA13_OFFSET 0
#define EFUSE_RDATA13_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG14_ADDR 0x0088
#define EFUSE_RDATA14_OFFSET 0
#define EFUSE_RDATA14_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_EFUSE_CFG15_ADDR 0x008c
#define EFUSE_RDATA15_OFFSET 0
#define EFUSE_RDATA15_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ANA_SEL_CFG0_ADDR 0x0090
#define RX_GLAN_SEL_OFFSET 5
#define RX_GLAN_SEL_MASK 0x00000020
#define DAC_DATA_SEL_OFFSET 4
#define DAC_DATA_SEL_MASK 0x00000010
#define ANA_DEBUG_SEL_OFFSET 0
#define ANA_DEBUG_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_PWM_COMP_SEL1_ADDR 0x0094
#define PWM5_COMP_IN2_SEL_OFFSET 28
#define PWM5_COMP_IN2_SEL_MASK 0xF0000000
#define PWM5_COMP_IN1_SEL_OFFSET 24
#define PWM5_COMP_IN1_SEL_MASK 0x0F000000
#define PWM4_COMP_IN2_SEL_OFFSET 20
#define PWM4_COMP_IN2_SEL_MASK 0x00F00000
#define PWM4_COMP_IN1_SEL_OFFSET 16
#define PWM4_COMP_IN1_SEL_MASK 0x000F0000
#define PWM3_COMP_IN2_SEL_OFFSET 12
#define PWM3_COMP_IN2_SEL_MASK 0x0000F000
#define PWM3_COMP_IN1_SEL_OFFSET 8
#define PWM3_COMP_IN1_SEL_MASK 0x00000F00
#define PWM2_COMP_IN2_SEL_OFFSET 4
#define PWM2_COMP_IN2_SEL_MASK 0x000000F0
#define PWM2_COMP_IN1_SEL_OFFSET 0
#define PWM2_COMP_IN1_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_PWM_COMP_SEL0_ADDR 0x0098
#define PWM1_COMP_IN2_SEL_OFFSET 12
#define PWM1_COMP_IN2_SEL_MASK 0x0000F000
#define PWM1_COMP_IN1_SEL_OFFSET 8
#define PWM1_COMP_IN1_SEL_MASK 0x00000F00
#define PWM0_COMP_IN2_SEL_OFFSET 4
#define PWM0_COMP_IN2_SEL_MASK 0x000000F0
#define PWM0_COMP_IN1_SEL_OFFSET 0
#define PWM0_COMP_IN1_SEL_MASK 0x0000000F

//-----------------------------------
#define CFG_PWM_SOC_EN_ADDR 0x009C
#define PWM_TBCLK_SYNC_OFFSET 12
#define PWM_TBCLK_SYNC_MASK 0x00001000
#define PWM5_SOCB_EN_OFFSET 11
#define PWM5_SOCB_EN_MASK 0x00000800
#define PWM5_SOCA_EN_OFFSET 10
#define PWM5_SOCA_EN_MASK 0x00000400
#define PWM4_SOCB_EN_OFFSET 9
#define PWM4_SOCB_EN_MASK 0x00000200
#define PWM4_SOCA_EN_OFFSET 8
#define PWM4_SOCA_EN_MASK 0x00000100
#define PWM3_SOCB_EN_OFFSET 7
#define PWM3_SOCB_EN_MASK 0x00000080
#define PWM3_SOCA_EN_OFFSET 6
#define PWM3_SOCA_EN_MASK 0x00000040
#define PWM2_SOCB_EN_OFFSET 5
#define PWM2_SOCB_EN_MASK 0x00000020
#define PWM2_SOCA_EN_OFFSET 4
#define PWM2_SOCA_EN_MASK 0x00000010
#define PWM1_SOCB_EN_OFFSET 3
#define PWM1_SOCB_EN_MASK 0x00000008
#define PWM1_SOCA_EN_OFFSET 2
#define PWM1_SOCA_EN_MASK 0x00000004
#define PWM0_SOCB_EN_OFFSET 1
#define PWM0_SOCB_EN_MASK 0x00000002
#define PWM0_SOCA_EN_OFFSET 0
#define PWM0_SOCA_EN_MASK 0x00000001

//-----------------------------------
#define CFG_I2S_SOFT_FORCE_START_ADDR 0x00A0
#define I2S_SOFT_TX_START_OFFSET 1
#define I2S_SOFT_TX_START_MASK 0x00000002
#define I2S_SOFT_RX_START_OFFSET 0
#define I2S_SOFT_RX_START_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GEN_SET_ADDR 0x00B0
#define MCLK_AUDIO_EB_SET_OFFSET 31
#define MCLK_AUDIO_EB_SET_MASK 0x80000000
#define IIS4_EB_SET_OFFSET 30
#define IIS4_EB_SET_MASK 0x40000000
#define SADC_EB_SET_OFFSET 29
#define SADC_EB_SET_MASK 0x20000000
#define IIS3_EB_SET_OFFSET 28
#define IIS3_EB_SET_MASK 0x10000000
#define PWM5_EB_SET_OFFSET 27
#define PWM5_EB_SET_MASK 0x08000000
#define PWM4_EB_SET_OFFSET 26
#define PWM4_EB_SET_MASK 0x04000000
#define PWM3_EB_SET_OFFSET 25
#define PWM3_EB_SET_MASK 0x02000000
#define PWM2_EB_SET_OFFSET 24
#define PWM2_EB_SET_MASK 0x01000000
#define PWM1_EB_SET_OFFSET 23
#define PWM1_EB_SET_MASK 0x00800000
#define PWM0_EB_SET_OFFSET 22
#define PWM0_EB_SET_MASK 0x00400000
#define IIS2_EB_SET_OFFSET 21
#define IIS2_EB_SET_MASK 0x00200000
#define IIS1_EB_SET_OFFSET 20
#define IIS1_EB_SET_MASK 0x00100000
#define IIS0_EB_SET_OFFSET 19
#define IIS0_EB_SET_MASK 0x00080000
#define ANA_REG_EB_SET_OFFSET 18
#define ANA_REG_EB_SET_MASK 0x00040000
#define DMA_HW_EB_SET_OFFSET 17
#define DMA_HW_EB_SET_MASK 0x00020000
#define UART_MEM_EB_SET_OFFSET 16
#define UART_MEM_EB_SET_MASK 0x00010000
#define UART_3_EB_SET_OFFSET 15
#define UART_3_EB_SET_MASK 0x00008000
#define CAN1_EB_SET_OFFSET 14
#define CAN1_EB_SET_MASK 0x00004000
#define WDG0_EB_SET_OFFSET 13
#define WDG0_EB_SET_MASK 0x00002000
#define SPI_S0_EB_SET_OFFSET 11
#define SPI_S0_EB_SET_MASK 0x00000800
#define SPI_M1_EB_SET_OFFSET 10
#define SPI_M1_EB_SET_MASK 0x00000400
#define SPI_M0_EB_SET_OFFSET 9
#define SPI_M0_EB_SET_MASK 0x00000200
#define CLKREG_EB_SET_OFFSET 8
#define CLKREG_EB_SET_MASK 0x00000100
#define CAN0_EB_SET_OFFSET 7
#define CAN0_EB_SET_MASK 0x00000080
#define PINREG_EB_SET_OFFSET 6
#define PINREG_EB_SET_MASK 0x00000040
#define UART_2_EB_SET_OFFSET 5
#define UART_2_EB_SET_MASK 0x00000020
#define UART_1_EB_SET_OFFSET 4
#define UART_1_EB_SET_MASK 0x00000010
#define INTC0_EB_SET_OFFSET 3
#define INTC0_EB_SET_MASK 0x00000008
#define GTMR0_EB_SET_OFFSET 2
#define GTMR0_EB_SET_MASK 0x00000004
#define GPIO_EB_SET_OFFSET 1
#define GPIO_EB_SET_MASK 0x00000002
#define UART_0_EB_SET_OFFSET 0
#define UART_0_EB_SET_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GEN_CLR_ADDR 0x00B4
#define MCLK_AUDIO_EB_CLR_OFFSET 31
#define MCLK_AUDIO_EB_CLR_MASK 0x80000000
#define IIS4_EB_CLR_OFFSET 30
#define IIS4_EB_CLR_MASK 0x40000000
#define SADC_EB_CLR_OFFSET 29
#define SADC_EB_CLR_MASK 0x20000000
#define IIS3_EB_CLR_OFFSET 28
#define IIS3_EB_CLR_MASK 0x10000000
#define PWM5_EB_CLR_OFFSET 27
#define PWM5_EB_CLR_MASK 0x08000000
#define PWM4_EB_CLR_OFFSET 26
#define PWM4_EB_CLR_MASK 0x04000000
#define PWM3_EB_CLR_OFFSET 25
#define PWM3_EB_CLR_MASK 0x02000000
#define PWM2_EB_CLR_OFFSET 24
#define PWM2_EB_CLR_MASK 0x01000000
#define PWM1_EB_CLR_OFFSET 23
#define PWM1_EB_CLR_MASK 0x00800000
#define PWM0_EB_CLR_OFFSET 22
#define PWM0_EB_CLR_MASK 0x00400000
#define IIS2_EB_CLR_OFFSET 21
#define IIS2_EB_CLR_MASK 0x00200000
#define IIS1_EB_CLR_OFFSET 20
#define IIS1_EB_CLR_MASK 0x00100000
#define IIS0_EB_CLR_OFFSET 19
#define IIS0_EB_CLR_MASK 0x00080000
#define ANA_REG_EB_CLR_OFFSET 18
#define ANA_REG_EB_CLR_MASK 0x00040000
#define DMA_HW_EB_CLR_OFFSET 17
#define DMA_HW_EB_CLR_MASK 0x00020000
#define UART_MEM_EB_CLR_OFFSET 16
#define UART_MEM_EB_CLR_MASK 0x00010000
#define UART_3_EB_CLR_OFFSET 15
#define UART_3_EB_CLR_MASK 0x00008000
#define CAN1_EB_CLR_OFFSET 14
#define CAN1_EB_CLR_MASK 0x00004000
#define WDG0_EB_CLR_OFFSET 13
#define WDG0_EB_CLR_MASK 0x00002000
#define SPI_S0_EB_CLR_OFFSET 11
#define SPI_S0_EB_CLR_MASK 0x00000800
#define SPI_M1_EB_CLR_OFFSET 10
#define SPI_M1_EB_CLR_MASK 0x00000400
#define SPI_M0_EB_CLR_OFFSET 9
#define SPI_M0_EB_CLR_MASK 0x00000200
#define CLKREG_EB_CLR_OFFSET 8
#define CLKREG_EB_CLR_MASK 0x00000100
#define CAN0_EB_CLR_OFFSET 7
#define CAN0_EB_CLR_MASK 0x00000080
#define PINREG_EB_CLR_OFFSET 6
#define PINREG_EB_CLR_MASK 0x00000040
#define UART_2_EB_CLR_OFFSET 5
#define UART_2_EB_CLR_MASK 0x00000020
#define UART_1_EB_CLR_OFFSET 4
#define UART_1_EB_CLR_MASK 0x00000010
#define INTC0_EB_CLR_OFFSET 3
#define INTC0_EB_CLR_MASK 0x00000008
#define GTMR0_EB_CLR_OFFSET 2
#define GTMR0_EB_CLR_MASK 0x00000004
#define GPIO_EB_CLR_OFFSET 1
#define GPIO_EB_CLR_MASK 0x00000002
#define UART_0_EB_CLR_OFFSET 0
#define UART_0_EB_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST0_SET_ADDR 0x00B8
#define IIS4_SOFT_RST_SET_OFFSET 30
#define IIS4_SOFT_RST_SET_MASK 0x40000000
#define SADC_SOFT_RST_SET_OFFSET 29
#define SADC_SOFT_RST_SET_MASK 0x20000000
#define IIS3_SOFT_RST_SET_OFFSET 28
#define IIS3_SOFT_RST_SET_MASK 0x10000000
#define PWM5_SOFT_RST_SET_OFFSET 27
#define PWM5_SOFT_RST_SET_MASK 0x08000000
#define PWM4_SOFT_RST_SET_OFFSET 26
#define PWM4_SOFT_RST_SET_MASK 0x04000000
#define PWM3_SOFT_RST_SET_OFFSET 25
#define PWM3_SOFT_RST_SET_MASK 0x02000000
#define PWM2_SOFT_RST_SET_OFFSET 24
#define PWM2_SOFT_RST_SET_MASK 0x01000000
#define PWM1_SOFT_RST_SET_OFFSET 23
#define PWM1_SOFT_RST_SET_MASK 0x00800000
#define PWM0_SOFT_RST_SET_OFFSET 22
#define PWM0_SOFT_RST_SET_MASK 0x00400000
#define IIS2_SOFT_RST_SET_OFFSET 21
#define IIS2_SOFT_RST_SET_MASK 0x00200000
#define IIS1_SOFT_RST_SET_OFFSET 20
#define IIS1_SOFT_RST_SET_MASK 0x00100000
#define IIS0_SOFT_RST_SET_OFFSET 19
#define IIS0_SOFT_RST_SET_MASK 0x00080000
#define ANA_REG_SOFT_RST_SET_OFFSET 18
#define ANA_REG_SOFT_RST_SET_MASK 0x00040000
#define DMA_HW_SOFT_RST_SET_OFFSET 17
#define DMA_HW_SOFT_RST_SET_MASK 0x00020000
#define UART_MEM_SOFT_RST_SET_OFFSET 16
#define UART_MEM_SOFT_RST_SET_MASK 0x00010000
#define UART_3_SOFT_RST_SET_OFFSET 15
#define UART_3_SOFT_RST_SET_MASK 0x00008000
#define CAN1_SOFT_RST_SET_OFFSET 14
#define CAN1_SOFT_RST_SET_MASK 0x00004000
#define WDG0_SOFT_RST_SET_OFFSET 13
#define WDG0_SOFT_RST_SET_MASK 0x00002000
#define SPI_S0_SOFT_RST_SET_OFFSET 11
#define SPI_S0_SOFT_RST_SET_MASK 0x00000800
#define SPI_M1_SOFT_RST_SET_OFFSET 10
#define SPI_M1_SOFT_RST_SET_MASK 0x00000400
#define SPI_M0_SOFT_RST_SET_OFFSET 9
#define SPI_M0_SOFT_RST_SET_MASK 0x00000200
#define CLKREG_SOFT_RST_SET_OFFSET 8
#define CLKREG_SOFT_RST_SET_MASK 0x00000100
#define CAN0_SOFT_RST_SET_OFFSET 7
#define CAN0_SOFT_RST_SET_MASK 0x00000080
#define PINREG_SOFT_RST_SET_OFFSET 6
#define PINREG_SOFT_RST_SET_MASK 0x00000040
#define UART_2_SOFT_RST_SET_OFFSET 5
#define UART_2_SOFT_RST_SET_MASK 0x00000020
#define UART_1_SOFT_RST_SET_OFFSET 4
#define UART_1_SOFT_RST_SET_MASK 0x00000010
#define INTC0_SOFT_RST_SET_OFFSET 3
#define INTC0_SOFT_RST_SET_MASK 0x00000008
#define GTMR0_SOFT_RST_SET_OFFSET 2
#define GTMR0_SOFT_RST_SET_MASK 0x00000004
#define GPIO_SOFT_RST_SET_OFFSET 1
#define GPIO_SOFT_RST_SET_MASK 0x00000002
#define UART_0_SOFT_RST_SET_OFFSET 0
#define UART_0_SOFT_RST_SET_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST0_CLR_ADDR 0x00BC
#define IIS4_SOFT_RST_CLR_OFFSET 30
#define IIS4_SOFT_RST_CLR_MASK 0x40000000
#define SADC_SOFT_RST_CLR_OFFSET 29
#define SADC_SOFT_RST_CLR_MASK 0x20000000
#define IIS3_SOFT_RST_CLR_OFFSET 28
#define IIS3_SOFT_RST_CLR_MASK 0x10000000
#define PWM5_SOFT_RST_CLR_OFFSET 27
#define PWM5_SOFT_RST_CLR_MASK 0x08000000
#define PWM4_SOFT_RST_CLR_OFFSET 26
#define PWM4_SOFT_RST_CLR_MASK 0x04000000
#define PWM3_SOFT_RST_CLR_OFFSET 25
#define PWM3_SOFT_RST_CLR_MASK 0x02000000
#define PWM2_SOFT_RST_CLR_OFFSET 24
#define PWM2_SOFT_RST_CLR_MASK 0x01000000
#define PWM1_SOFT_RST_CLR_OFFSET 23
#define PWM1_SOFT_RST_CLR_MASK 0x00800000
#define PWM0_SOFT_RST_CLR_OFFSET 22
#define PWM0_SOFT_RST_CLR_MASK 0x00400000
#define IIS2_SOFT_RST_CLR_OFFSET 21
#define IIS2_SOFT_RST_CLR_MASK 0x00200000
#define IIS1_SOFT_RST_CLR_OFFSET 20
#define IIS1_SOFT_RST_CLR_MASK 0x00100000
#define IIS0_SOFT_RST_CLR_OFFSET 19
#define IIS0_SOFT_RST_CLR_MASK 0x00080000
#define ANA_REG_SOFT_RST_CLR_OFFSET 18
#define ANA_REG_SOFT_RST_CLR_MASK 0x00040000
#define DMA_HW_SOFT_RST_CLR_OFFSET 17
#define DMA_HW_SOFT_RST_CLR_MASK 0x00020000
#define UART_MEM_SOFT_RST_CLR_OFFSET 16
#define UART_MEM_SOFT_RST_CLR_MASK 0x00010000
#define UART_3_SOFT_RST_CLR_OFFSET 15
#define UART_3_SOFT_RST_CLR_MASK 0x00008000
#define CAN1_SOFT_RST_CLR_OFFSET 14
#define CAN1_SOFT_RST_CLR_MASK 0x00004000
#define WDG0_SOFT_RST_CLR_OFFSET 13
#define WDG0_SOFT_RST_CLR_MASK 0x00002000
#define SPI_S0_SOFT_RST_CLR_OFFSET 11
#define SPI_S0_SOFT_RST_CLR_MASK 0x00000800
#define SPI_M1_SOFT_RST_CLR_OFFSET 10
#define SPI_M1_SOFT_RST_CLR_MASK 0x00000400
#define SPI_M0_SOFT_RST_CLR_OFFSET 9
#define SPI_M0_SOFT_RST_CLR_MASK 0x00000200
#define CLKREG_SOFT_RST_CLR_OFFSET 8
#define CLKREG_SOFT_RST_CLR_MASK 0x00000100
#define CAN0_SOFT_RST_CLR_OFFSET 7
#define CAN0_SOFT_RST_CLR_MASK 0x00000080
#define PINREG_SOFT_RST_CLR_OFFSET 6
#define PINREG_SOFT_RST_CLR_MASK 0x00000040
#define UART_2_SOFT_RST_CLR_OFFSET 5
#define UART_2_SOFT_RST_CLR_MASK 0x00000020
#define UART_1_SOFT_RST_CLR_OFFSET 4
#define UART_1_SOFT_RST_CLR_MASK 0x00000010
#define INTC0_SOFT_RST_CLR_OFFSET 3
#define INTC0_SOFT_RST_CLR_MASK 0x00000008
#define GTMR0_SOFT_RST_CLR_OFFSET 2
#define GTMR0_SOFT_RST_CLR_MASK 0x00000004
#define GPIO_SOFT_RST_CLR_OFFSET 1
#define GPIO_SOFT_RST_CLR_MASK 0x00000002
#define UART_0_SOFT_RST_CLR_OFFSET 0
#define UART_0_SOFT_RST_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GEN1_SET_ADDR 0x00C0
#define FMST_EB_SET_OFFSET 17
#define FMST_EB_SET_MASK 0x00020000
#define AUDIO_WK_EB_SET_OFFSET 16
#define AUDIO_WK_EB_SET_MASK 0x00010000
#define SPINLOCK_EB_SET_OFFSET 15
#define SPINLOCK_EB_SET_MASK 0x00008000
#define GTMR2_EB_SET_OFFSET 14
#define GTMR2_EB_SET_MASK 0x00004000
#define INTC2_EB_SET_OFFSET 13
#define INTC2_EB_SET_MASK 0x00002000
#define WDG2_EB_SET_OFFSET 12
#define WDG2_EB_SET_MASK 0x00001000
#define I2C0_S_EB_SET_OFFSET 11
#define I2C0_S_EB_SET_MASK 0x00000800
#define I2C2_EB_SET_OFFSET 10
#define I2C2_EB_SET_MASK 0x00000400
#define LEDC_EB_SET_OFFSET 9
#define LEDC_EB_SET_MASK 0x00000200
#define I2C1_EB_SET_OFFSET 8
#define I2C1_EB_SET_MASK 0x00000100
#define I2C0_EB_SET_OFFSET 7
#define I2C0_EB_SET_MASK 0x00000080
#define SIG_PWM3_EB_SET_OFFSET 6
#define SIG_PWM3_EB_SET_MASK 0x00000040
#define SIG_PWM2_EB_SET_OFFSET 5
#define SIG_PWM2_EB_SET_MASK 0x00000020
#define SIG_PWM1_EB_SET_OFFSET 4
#define SIG_PWM1_EB_SET_MASK 0x00000010
#define SIG_PWM0_EB_SET_OFFSET 3
#define SIG_PWM0_EB_SET_MASK 0x00000008
#define GMTX_EB_SET_OFFSET 2
#define GMTX_EB_SET_MASK 0x00000004

//-----------------------------------
#define CFG_APB_GLB_GEN1_CLR_ADDR 0x00C4
#define FMST_EB_CLR_OFFSET 17
#define FMST_EB_CLR_MASK 0x00020000
#define AUDIO_WK_EB_CLR_OFFSET 16
#define AUDIO_WK_EB_CLR_MASK 0x00010000
#define SPINLOCK_EB_CLR_OFFSET 15
#define SPINLOCK_EB_CLR_MASK 0x00008000
#define GTMR2_EB_CLR_OFFSET 14
#define GTMR2_EB_CLR_MASK 0x00004000
#define INTC2_EB_CLR_OFFSET 13
#define INTC2_EB_CLR_MASK 0x00002000
#define WDG2_EB_CLR_OFFSET 12
#define WDG2_EB_CLR_MASK 0x00001000
#define I2C0_S_EB_CLR_OFFSET 11
#define I2C0_S_EB_CLR_MASK 0x00000800
#define I2C2_EB_CLR_OFFSET 10
#define I2C2_EB_CLR_MASK 0x00000400
#define LEDC_EB_CLR_OFFSET 9
#define LEDC_EB_CLR_MASK 0x00000200
#define I2C1_EB_CLR_OFFSET 8
#define I2C1_EB_CLR_MASK 0x00000100
#define I2C0_EB_CLR_OFFSET 7
#define I2C0_EB_CLR_MASK 0x00000080
#define SIG_PWM3_EB_CLR_OFFSET 6
#define SIG_PWM3_EB_CLR_MASK 0x00000040
#define SIG_PWM2_EB_CLR_OFFSET 5
#define SIG_PWM2_EB_CLR_MASK 0x00000020
#define SIG_PWM1_EB_CLR_OFFSET 4
#define SIG_PWM1_EB_CLR_MASK 0x00000010
#define SIG_PWM0_EB_CLR_OFFSET 3
#define SIG_PWM0_EB_CLR_MASK 0x00000008
#define GMTX_EB_CLR_OFFSET 2
#define GMTX_EB_CLR_MASK 0x00000004

//-----------------------------------
#define CFG_APB_GLB_GRST1_SET_ADDR 0x00C8
#define FMST_SOFT_RST_SET_OFFSET 17
#define FMST_SOFT_RST_SET_MASK 0x00020000
#define AUDIO_WK_SOFT_RST_SET_OFFSET 16
#define AUDIO_WK_SOFT_RST_SET_MASK 0x00010000
#define SPINLOCK_SOFT_RST_SET_OFFSET 15
#define SPINLOCK_SOFT_RST_SET_MASK 0x00008000
#define GTMR2_SOFT_RST_SET_OFFSET 14
#define GTMR2_SOFT_RST_SET_MASK 0x00004000
#define WDG2_SOFT_RST_SET_OFFSET 13
#define WDG2_SOFT_RST_SET_MASK 0x00002000
#define INTC2_SOFT_RST_SET_OFFSET 12
#define INTC2_SOFT_RST_SET_MASK 0x00001000
#define I2C0_S_SOFT_RST_SET_OFFSET 11
#define I2C0_S_SOFT_RST_SET_MASK 0x00000800
#define I2C2_SOFT_RST_SET_OFFSET 10
#define I2C2_SOFT_RST_SET_MASK 0x00000400
#define LEDC_SOFT_RST_SET_OFFSET 9
#define LEDC_SOFT_RST_SET_MASK 0x00000200
#define I2C1_SOFT_RST_SET_OFFSET 8
#define I2C1_SOFT_RST_SET_MASK 0x00000100
#define I2C0_SOFT_RST_SET_OFFSET 7
#define I2C0_SOFT_RST_SET_MASK 0x00000080
#define SIG_PWM3_SOFT_RST_SET_OFFSET 6
#define SIG_PWM3_SOFT_RST_SET_MASK 0x00000040
#define SIG_PWM2_SOFT_RST_SET_OFFSET 5
#define SIG_PWM2_SOFT_RST_SET_MASK 0x00000020
#define SIG_PWM1_SOFT_RST_SET_OFFSET 4
#define SIG_PWM1_SOFT_RST_SET_MASK 0x00000010
#define SIG_PWM0_SOFT_RST_SET_OFFSET 3
#define SIG_PWM0_SOFT_RST_SET_MASK 0x00000008
#define GMTX_SOFT_RST_SET_OFFSET 2
#define GMTX_SOFT_RST_SET_MASK 0x00000004

//-----------------------------------
#define CFG_APB_GLB_GRST1_CLR_ADDR 0x00CC
#define FMST_SOFT_RST_CLR_OFFSET 17
#define FMST_SOFT_RST_CLR_MASK 0x00020000
#define AUDIO_WK_SOFT_RST_CLR_OFFSET 16
#define AUDIO_WK_SOFT_RST_CLR_MASK 0x00010000
#define SPINLOCK_SOFT_RST_CLR_OFFSET 15
#define SPINLOCK_SOFT_RST_CLR_MASK 0x00008000
#define GTMR2_SOFT_RST_CLR_OFFSET 14
#define GTMR2_SOFT_RST_CLR_MASK 0x00004000
#define WDG2_SOFT_RST_CLR_OFFSET 13
#define WDG2_SOFT_RST_CLR_MASK 0x00002000
#define INTC2_SOFT_RST_CLR_OFFSET 12
#define INTC2_SOFT_RST_CLR_MASK 0x00001000
#define I2C0_S_SOFT_RST_CLR_OFFSET 11
#define I2C0_S_SOFT_RST_CLR_MASK 0x00000800
#define I2C2_SOFT_RST_CLR_OFFSET 10
#define I2C2_SOFT_RST_CLR_MASK 0x00000400
#define LEDC_SOFT_RST_CLR_OFFSET 9
#define LEDC_SOFT_RST_CLR_MASK 0x00000200
#define I2C1_SOFT_RST_CLR_OFFSET 8
#define I2C1_SOFT_RST_CLR_MASK 0x00000100
#define I2C0_SOFT_RST_CLR_OFFSET 7
#define I2C0_SOFT_RST_CLR_MASK 0x00000080
#define SIG_PWM3_SOFT_RST_CLR_OFFSET 6
#define SIG_PWM3_SOFT_RST_CLR_MASK 0x00000040
#define SIG_PWM2_SOFT_RST_CLR_OFFSET 5
#define SIG_PWM2_SOFT_RST_CLR_MASK 0x00000020
#define SIG_PWM1_SOFT_RST_CLR_OFFSET 4
#define SIG_PWM1_SOFT_RST_CLR_MASK 0x00000010
#define SIG_PWM0_SOFT_RST_CLR_OFFSET 3
#define SIG_PWM0_SOFT_RST_CLR_MASK 0x00000008
#define GMTX_SOFT_RST_CLR_OFFSET 2
#define GMTX_SOFT_RST_CLR_MASK 0x00000004

//-----------------------------------
#define CFG_APB_COMMON_CONFIG_ADDR 0x00D0
#define TICK_1M_REF_LIMIT_OFFSET 0
#define TICK_1M_REF_LIMIT_MASK 0x0000001F

//HW module read/write macro
#define APB_GLB_READ_REG(addr) SOC_READ_REG(APB_GLB_BASEADDR + addr)
#define APB_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(APB_GLB_BASEADDR + addr,value)