39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
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//-----------------------------------
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#define CFG_ITR_ITR_SRC_CTRL0_ADDR 0x0000
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#define ITR_SRC_WIDTH_OFFSET 16
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#define ITR_SRC_WIDTH_MASK 0x07FF0000
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#define ITR_SRC_HEIGHT_OFFSET 0
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#define ITR_SRC_HEIGHT_MASK 0x000007FF
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//-----------------------------------
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#define CFG_ITR_ITR_SRC_CTRL1_ADDR 0x0004
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#define ITR_SRC_BASE_ADDRESS_OFFSET 0
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#define ITR_SRC_BASE_ADDRESS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ITR_ITR_DST_CTRL0_ADDR 0x0008
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#define ITR_CLOCKWISE_OFFSET 0
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#define ITR_CLOCKWISE_MASK 0x00000001
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//-----------------------------------
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#define CFG_ITR_ITR_DST_CTRL1_ADDR 0x000C
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#define ITR_DST_BASE_ADDRESS_OFFSET 0
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#define ITR_DST_BASE_ADDRESS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_ITR_ITR_GLB_CTRL_ADDR 0x0010
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#define ITR_STATUS_OFFSET 31
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#define ITR_STATUS_MASK 0x80000000
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#define ITR_START_OFFSET 0
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#define ITR_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_ITR_ITR_INT_CLR_ADDR 0x0014
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#define ITR_INT_CLR_OFFSET 0
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#define ITR_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define RGF_TRANSPOSE_READ_REG(addr) SOC_READ_REG(RGF_TRANSPOSE_BASEADDR + addr)
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#define RGF_TRANSPOSE_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_TRANSPOSE_BASEADDR + addr,value)
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