62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
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//-----------------------------------
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#define CFG_APB_RVER_ADDR 0x0000
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#define APB_RF_VER_OFFSET 0
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#define APB_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_APB_GLB_GEN0_ADDR 0x0004
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#define CLKEB_OFFSET 8
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#define CLKEB_MASK 0x00000100
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#define GTMR1_EB_OFFSET 7
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#define GTMR1_EB_MASK 0x00000080
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#define PINEB_OFFSET 6
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#define PINEB_MASK 0x00000040
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#define UART_2_EB_OFFSET 5
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#define UART_2_EB_MASK 0x00000020
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#define UART_1_EB_OFFSET 4
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#define UART_1_EB_MASK 0x00000010
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#define INTC_EB_OFFSET 3
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#define INTC_EB_MASK 0x00000008
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#define GTMR0_EB_OFFSET 2
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#define GTMR0_EB_MASK 0x00000004
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#define GPIO_EB_OFFSET 1
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#define GPIO_EB_MASK 0x00000002
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#define UART_0_EB_OFFSET 0
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#define UART_0_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_GLB_GRST0_ADDR 0x0008
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#define CLKSOFT_RST_OFFSET 8
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#define CLKSOFT_RST_MASK 0x00000100
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#define GTMR1_SOFT_RST_OFFSET 7
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#define GTMR1_SOFT_RST_MASK 0x00000080
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#define PINSOFT_RST_OFFSET 6
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#define PINSOFT_RST_MASK 0x00000040
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#define UART_2_SOFT_RST_OFFSET 5
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#define UART_2_SOFT_RST_MASK 0x00000020
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#define UART_1_SOFT_RST_OFFSET 4
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#define UART_1_SOFT_RST_MASK 0x00000010
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#define INTC_SOFT_RST_OFFSET 3
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#define INTC_SOFT_RST_MASK 0x00000008
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#define GTMR0_SOFT_RST_OFFSET 2
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#define GTMR0_SOFT_RST_MASK 0x00000004
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#define GPIO_SOFT_RST_OFFSET 1
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#define GPIO_SOFT_RST_MASK 0x00000002
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#define UART_0_SOFT_RST_OFFSET 0
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#define UART_0_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_APB_GPIO_CFG_ADDR 0x000c
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#define GPIO_ENA_CFG_OFFSET 0
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#define GPIO_ENA_CFG_MASK 0x000001FF
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//-----------------------------------
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#define CFG_APB_GLB_CTRL_ADDR 0x0010
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#define GLB_CTRL0_OFFSET 0
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#define GLB_CTRL0_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define APB_GLB_READ_REG(addr) SOC_READ_REG(APB_GLB_BASEADDR + addr)
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#define APB_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(APB_GLB_BASEADDR + addr,value)
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