89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
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//-----------------------------------
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#define CFG_EPARSER_REG_RVER_ADDR 0x0
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#define EPARSER_RF_VER_OFFSET 0
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#define EPARSER_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_EPARSER_DMA_CFG_ADDR 0x4
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#define OUT_BIT_ORDER_SEL_OFFSET 7
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#define OUT_BIT_ORDER_SEL_MASK 0x00000080
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#define OUT_BYTE_ORDER_SEL_OFFSET 6
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#define OUT_BYTE_ORDER_SEL_MASK 0x00000040
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#define IN_BIT_ORDER_SEL_OFFSET 5
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#define IN_BIT_ORDER_SEL_MASK 0x00000020
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#define IN_BYTE_ORDER_SEL_OFFSET 4
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#define IN_BYTE_ORDER_SEL_MASK 0x00000010
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#define DMA_STOP_OFFSET 2
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#define DMA_STOP_MASK 0x00000004
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#define DMA_RESTART_OFFSET 1
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#define DMA_RESTART_MASK 0x00000002
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#define DMA_START_OFFSET 0
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#define DMA_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_LINK_ADDR_CFG_ADDR 0x8
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#define DMA_LINK_ADDR_OFFSET 0
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#define DMA_LINK_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_INT_RAW_ADDR 0x10
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#define EDMA_ALL_DECR_INT_RAW_OFFSET 1
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#define EDMA_ALL_DECR_INT_RAW_MASK 0x00000002
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#define EDMA_CURR_DECR_INT_RAW_OFFSET 0
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#define EDMA_CURR_DECR_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_INT_ST_ADDR 0x14
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#define EDMA_ALL_DECR_INT_ST_OFFSET 1
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#define EDMA_ALL_DECR_INT_ST_MASK 0x00000002
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#define EDMA_CURR_DECR_INT_ST_OFFSET 0
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#define EDMA_CURR_DECR_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_INT_ENA_ADDR 0x18
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#define EDMA_ALL_DECR_INT_ENA_OFFSET 1
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#define EDMA_ALL_DECR_INT_ENA_MASK 0x00000002
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#define EDMA_CURR_DECR_INT_ENA_OFFSET 0
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#define EDMA_CURR_DECR_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_INT_CLR_ADDR 0x1C
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#define EDMA_ALL_DECR_INT_CLR_OFFSET 1
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#define EDMA_ALL_DECR_INT_CLR_MASK 0x00000002
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#define EDMA_CURR_DECR_INT_CLR_OFFSET 0
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#define EDMA_CURR_DECR_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_DMA_RESET_ADDR_CFG_ADDR 0x20
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#define EDMA_RESET_DECR_ADDR_OFFSET 0
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#define EDMA_RESET_DECR_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_DMA_DBG_BUS_ADDR 0x24
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#define DMA_SIG_DBG_BUS_OFFSET 0
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#define DMA_SIG_DBG_BUS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PARSER_ACTION_ADDR 0x28
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#define REG_HEAD_LEN_VLD_OFFSET 25
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#define REG_HEAD_LEN_VLD_MASK 0x02000000
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#define REG_HEAD_LEN_OFFSET 18
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#define REG_HEAD_LEN_MASK 0x01FC0000
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#define REG_ACL_HIT_L2_OFFSET 17
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#define REG_ACL_HIT_L2_MASK 0x00020000
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#define REG_ACL_ACTION_L2_OFFSET 12
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#define REG_ACL_ACTION_L2_MASK 0x0001F000
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#define REG_ACL_HIT_L3_OFFSET 11
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#define REG_ACL_HIT_L3_MASK 0x00000800
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#define REG_ACL_ACTION_L3_OFFSET 6
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#define REG_ACL_ACTION_L3_MASK 0x000007C0
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#define REG_ACL_HIT_LU_OFFSET 5
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#define REG_ACL_HIT_LU_MASK 0x00000020
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#define REG_ACL_ACTION_LU_OFFSET 0
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#define REG_ACL_ACTION_LU_MASK 0x0000001F
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//HW module read/write macro
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#define EPARSER_READ_REG(addr) SOC_READ_REG(EPARSER_BASEADDR + addr)
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#define EPARSER_WRITE_REG(addr,value) SOC_WRITE_REG(EPARSER_BASEADDR + addr,value)
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