93 lines
3.2 KiB
C
93 lines
3.2 KiB
C
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_A_CFG0_ADDR 0x00
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#define CMM_MATRIX_A_IS_DIAGONAL_OFFSET 31
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#define CMM_MATRIX_A_IS_DIAGONAL_MASK 0x80000000
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#define CMM_MATRIX_A_IS_REAL_OFFSET 15
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#define CMM_MATRIX_A_IS_REAL_MASK 0x00008000
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#define CMM_MATRIX_A_COL_SIZE_OFFSET 8
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#define CMM_MATRIX_A_COL_SIZE_MASK 0x00007F00
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#define CMM_MATRIX_A_ROW_SIZE_OFFSET 0
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#define CMM_MATRIX_A_ROW_SIZE_MASK 0x0000007F
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_A_CFG1_ADDR 0x04
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#define CMM_MATRIX_A_START_ADDRESS_OFFSET 0
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#define CMM_MATRIX_A_START_ADDRESS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_A_CFG2_ADDR 0x08
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#define CMM_MATRIX_A_SIZE_OFFSET 0
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#define CMM_MATRIX_A_SIZE_MASK 0x000003FF
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_B_CFG0_ADDR 0x0C
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#define CMM_MATRIX_B_IS_DIAGONAL_OFFSET 31
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#define CMM_MATRIX_B_IS_DIAGONAL_MASK 0x80000000
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#define CMM_MATRIX_B_IS_REAL_OFFSET 15
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#define CMM_MATRIX_B_IS_REAL_MASK 0x00008000
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#define CMM_MATRIX_B_COL_SIZE_OFFSET 8
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#define CMM_MATRIX_B_COL_SIZE_MASK 0x00007F00
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#define CMM_MATRIX_B_ROW_SIZE_OFFSET 0
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#define CMM_MATRIX_B_ROW_SIZE_MASK 0x0000007F
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_B_CFG1_ADDR 0x10
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#define CMM_MATRIX_B_START_ADDRESS_OFFSET 0
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#define CMM_MATRIX_B_START_ADDRESS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CMM_CMM_MATRIX_B_CFG2_ADDR 0x14
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#define CMM_MATRIX_B_SIZE_OFFSET 0
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#define CMM_MATRIX_B_SIZE_MASK 0x000003FF
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//-----------------------------------
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#define CFG_CMM_CMM_CFG0_ADDR 0x18
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#define CMM_FORCE_ON_OFFSET 31
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#define CMM_FORCE_ON_MASK 0x80000000
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#define CMM_NUM_MULTIPLICATION_OFFSET 16
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#define CMM_NUM_MULTIPLICATION_MASK 0x7FFF0000
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#define CMM_FP_RND_OFFSET 0
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#define CMM_FP_RND_MASK 0x00000007
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//-----------------------------------
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#define CFG_CMM_CMM_CFG1_ADDR 0x1C
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#define CMM_NUM_OPERATOR_OFFSET 14
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#define CMM_NUM_OPERATOR_MASK 0x00004000
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#define CMM_OP3_CTRL_OFFSET 10
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#define CMM_OP3_CTRL_MASK 0x00003C00
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#define CMM_OP2_CTRL_OFFSET 6
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#define CMM_OP2_CTRL_MASK 0x000003C0
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#define CMM_OP1_CTRL_OFFSET 3
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#define CMM_OP1_CTRL_MASK 0x00000038
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#define CMM_OP0_CTRL_OFFSET 0
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#define CMM_OP0_CTRL_MASK 0x00000007
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//-----------------------------------
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#define CFG_CMM_CMM_CFG2_ADDR 0x20
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#define CMM_RESULT_START_ADDRESS_OFFSET 0
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#define CMM_RESULT_START_ADDRESS_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CMM_CMM_STATUS_ADDR 0x24
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#define CMM_COMPLETE_COUNT_OFFSET 16
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#define CMM_COMPLETE_COUNT_MASK 0x7FFF0000
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#define CMM_COMPLETE_OFFSET 0
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#define CMM_COMPLETE_MASK 0x00000001
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//-----------------------------------
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#define CFG_CMM_CMM_START_ADDR 0x28
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#define CMM_CMM_START_TRIGGER_OFFSET 0
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#define CMM_CMM_START_TRIGGER_MASK 0x00000001
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//-----------------------------------
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#define CFG_CMM_CMM_INT_CLR_ADDR 0x2C
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#define CMM_CMM_INT_CLR_OFFSET 0
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#define CMM_CMM_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define RGF_CMM0_READ_REG(addr) SOC_READ_REG(RGF_CMM0_BASEADDR + addr)
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#define RGF_CMM0_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CMM0_BASEADDR + addr,value)
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#define RGF_CMM1_READ_REG(addr) SOC_READ_REG(RGF_CMM1_BASEADDR + addr)
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#define RGF_CMM1_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CMM1_BASEADDR + addr,value)
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