70 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			70 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
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								#define SFC_RF_BASEADDR 0x52000100
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								//-----------------------------------
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								#define CFG_SFC_RVER_ADDR 0x0000
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								#define SFC_RF_VER_OFFSET 0
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								#define SFC_RF_VER_MASK 0x0000FFFF
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								//-----------------------------------
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								#define CFG_SFC_CMD0_ADDR 0x0004
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								#define SW_SFC_ENA_OFFSET 31
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								#define SW_SFC_ENA_MASK 0x80000000
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								#define SW_SFC_DLEN_OFFSET 16
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								#define SW_SFC_DLEN_MASK 0x01FF0000
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								#define SW_SFC_CMODE_OFFSET 8
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								#define SW_SFC_CMODE_MASK 0x0000FF00
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								#define SW_SFC_MODE_OFFSET 0
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								#define SW_SFC_MODE_MASK 0x00000003
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								//-----------------------------------
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								#define CFG_SFC_CMD1_ADDR 0x0008
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								#define SW_SFC_CMD_OFFSET 24
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								#define SW_SFC_CMD_MASK 0xFF000000
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								#define SW_SFC_ADDR_OFFSET 0
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								#define SW_SFC_ADDR_MASK 0x00FFFFFF
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								//-----------------------------------
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								#define CFG_SFC_CFG0_ADDR 0x000c
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								#define EMC_CRYPT_MODE_OFFSET 4
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								#define EMC_CRYPT_MODE_MASK 0x00000010
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								#define CACHE_RD_MODE_OFFSET 0
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								#define CACHE_RD_MODE_MASK 0x00000007
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								//-----------------------------------
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								#define CFG_SFC_CFG1_ADDR 0x0010
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								#define PE_WAIT_TIME_OFFSET 0
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								#define PE_WAIT_TIME_MASK 0xFFFFFFFF
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								//-----------------------------------
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								#define CFG_SFC_CFG2_ADDR 0x00014
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								#define RESUME_WAIT_TIME_OFFSET 16
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								#define RESUME_WAIT_TIME_MASK 0x03FF0000
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								#define SUS_WAIT_TIME_OFFSET 0
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								#define SUS_WAIT_TIME_MASK 0x0000FFFF
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								//-----------------------------------
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								#define CFG_SFC_STS0_ADDR 0x0018
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								#define SFC_FSM_STATE_OFFSET 4
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								#define SFC_FSM_STATE_MASK 0x000000F0
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								#define SPI_FSM_STATE_OFFSET 0
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								#define SPI_FSM_STATE_MASK 0x00000007
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								//-----------------------------------
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								#define CFG_SFC_RDATA_ADDR 0x001c
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								#define SW_SFC_RDATA_OFFSET 0
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								#define SW_SFC_RDATA_MASK 0xFFFFFFFF
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								//-----------------------------------
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								#define CFG_SFC_WDATA_ADDR 0x0020
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								#define SW_SFC_WDATA_OFFSET 0
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								#define SW_SFC_WDATA_MASK 0xFFFFFFFF
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								//-----------------------------------
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								#define CFG_SFC_DBG_ADDR 0x0024
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								#define SFC_CLK_FORCE_OUT_OFFSET 0
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								#define SFC_CLK_FORCE_OUT_MASK 0x00000001
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								//HW module read/write macro
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								#define SFC_RF_READ_REG(addr) SOC_READ_REG(SFC_RF_BASEADDR + addr)
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								#define SFC_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SFC_RF_BASEADDR + addr,value)
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