204 lines
6.8 KiB
C
204 lines
6.8 KiB
C
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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#include "chip_reg_base.h"
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#include "hw_reg_api.h"
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#include "phy_rx_fd_reg.h"
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#include "phy_reg.h"
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#include "tx_entry.h"
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#include "mac_reset.h"
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#include "mac_hwq_reg.h"
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#include "mac_sys_reg.h"
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#include "mac_rx_reg.h"
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#include "mac_tmr_reg.h"
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#include "iot_config.h"
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#include "plc_protocol.h"
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#include "hw_rx.h"
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#include "clk.h"
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#include "os_mem.h"
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void phy_rx_path_init()
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{
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uint32_t tmp = 0;
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#if IOT_RATE_MODE_RX == IOT_SUPPORT_RATE_SR_QR || \
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IOT_RATE_MODE_RX == IOT_SUPPORT_RATE_QR
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phy_qr_common_init();
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#endif
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/* fc err to mac */
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SEND_MAC_CTRL_ADDR);
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REG_FIELD_SET(SW_ALWAYS_SEND_FC, tmp, 1);
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REG_FIELD_SET(SW_ALWAYS_SEND_PB, tmp, 1);
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//REG_FIELD_SET(SW_FC_CRC_ERR_CTRL, tmp, 1);
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PHY_RX_FD_WRITE_REG(CFG_BB_SEND_MAC_CTRL_ADDR,tmp);
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#if MAC_TX_TEST_ID == MAC_TX_GP_EXT
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/* mix en */
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phy_mix_flag_set(true);
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tmp = PHY_RX_FD_READ_REG(CFG_BB_SEND_MAC_CTRL_ADDR);
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REG_FIELD_SET(SW_ALWAYS_SEND_FC, tmp, 0);
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PHY_RX_FD_WRITE_REG(CFG_BB_SEND_MAC_CTRL_ADDR, tmp);
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#if IOT_PLC_PHY_BAND_DFT == IOT_SUPPORT_TONE_80_1228
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phy_rxfd_rate0_det(80,1228);
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phy_rxfd_rate1_det(80,1228);
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#endif
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#endif
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}
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void mac_rx_path_init()
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{
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uint32_t tmp = 0;
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uint32_t symbnum_ppb = 0;
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uint32_t fl_ppb = 0;
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/* enable packets receive */
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tmp = RGF_RX_READ_REG(CFG_RX_FILTER_0_ADDR);
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//REG_FIELD_SET(CFG_FC_CRCERR_FILTER_DIS, tmp, 1);
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REG_FIELD_SET(CFG_NID_FILTER_DIS, tmp, 1);
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REG_FIELD_SET(CFG_MPDU_DTEI_FILTER_DIS, tmp, 1);
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REG_FIELD_SET(CFG_BEACON_PHASE_FILTER_DIS, tmp, 1);
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RGF_RX_WRITE_REG(CFG_RX_FILTER_0_ADDR, tmp);
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/* config my nid */
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tmp = RGF_MAC_READ_REG(CFG_MYNID_ADDR);
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REG_FIELD_SET(CFG_MYNID, tmp, PHY_TXRX_NID_VAL);
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RGF_MAC_WRITE_REG(CFG_MYNID_ADDR, tmp);
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/* tei cfg */
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RGF_MAC_WRITE_REG(CFG_MYTEI_ADDR, 2);
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/* delete timeout for long pkt */
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tmp = RGF_RX_READ_REG(CFG_RX_TIMEOUT_1_ADDR);
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REG_FIELD_SET(CFG_RX_PB_TIMEOUT, tmp, 2000000);
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RGF_RX_WRITE_REG(CFG_RX_TIMEOUT_1_ADDR, tmp);
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/* pb framelength for gp */
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if(PHY_PROTO_TYPE_GET() == PLC_PROTO_TYPE_GP){
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/* tmi0 band0 */
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symbnum_ppb = phy_get_sym_per_pb(PHY_PROTO_TYPE_GET(), 0, 0, 0, 0);
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fl_ppb = (uint32_t)(FRAME_LENGTH_PER_PB_GP(symbnum_ppb, GI_STD_ROBO)/1.28);
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tmp = RGF_RX_READ_REG(CFG_TMI0_BAND0_ADDR);
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REG_FIELD_SET(CFG_TMI0_BAND0_PBFL,tmp,fl_ppb);
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RGF_RX_WRITE_REG(CFG_TMI0_BAND0_ADDR,tmp);
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/* tmi1 band0 */
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symbnum_ppb = phy_get_sym_per_pb(PHY_PROTO_TYPE_GET(), 0, 1, 0, 0);
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fl_ppb = (uint32_t)(FRAME_LENGTH_PER_PB_GP(symbnum_ppb, GI_HS_ROBO)/1.28);
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tmp = RGF_RX_READ_REG(CFG_TMI1_BAND0_ADDR);
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REG_FIELD_SET(CFG_TMI1_BAND0_PBFL,tmp,fl_ppb);
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RGF_RX_WRITE_REG(CFG_TMI1_BAND0_ADDR,tmp);
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/* tmi2 band0 */
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symbnum_ppb = phy_get_sym_per_pb(PHY_PROTO_TYPE_GET(), 0, 2, 0, 0);
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fl_ppb = \
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(uint32_t)(FRAME_LENGTH_PER_PB_GP(symbnum_ppb, GI_MINI_ROBO)/1.28);
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tmp = RGF_RX_READ_REG(CFG_TMI2_BAND0_ADDR);
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REG_FIELD_SET(CFG_TMI2_BAND0_PBFL,tmp,fl_ppb);
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RGF_RX_WRITE_REG(CFG_TMI2_BAND0_ADDR,tmp);
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/* mix en from mac in the future */
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tmp = RGF_MAC_READ_REG(CFG_GP_CTRL_ADDR);
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REG_FIELD_SET(CFG_GP_PB_SIZE_SEL, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_GP_CTRL_ADDR,tmp);
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/* fix pld gi1 */
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if(glb_cfg.tmi == 0 || glb_cfg.tmi == 1)
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{
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phy_pld_gi1_set(GI_HS_ROBO);
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}
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else if(glb_cfg.tmi == 2)
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{
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phy_pld_gi1_set(GI_MINI_ROBO);
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}
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}
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/* Multi Rate */
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tmp = RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR);
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REG_FIELD_SET(CFG_PHY_RX_RATE_MODE_FORCE_EN, tmp, 1);
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REG_FIELD_SET(CFG_PHY_RX_RATE_MODE, tmp, IOT_RATE_MODE_RX);
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RGF_MAC_WRITE_REG(CFG_PHY_FORCE_0_ADDR,tmp);
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/* mac tx init */
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/* enable DCU debug mode */
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tmp = RGF_HWQ_READ_REG(CFG_SCH_ADDR);
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REG_FIELD_SET(CFG_HWQ_DBG_MODE, tmp, 1); // debug enable
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RGF_HWQ_WRITE_REG(CFG_SCH_ADDR, tmp);
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/* set hwq 0 's config */
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/* set hwq0's type, cap */
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tmp = RGF_HWQ_READ_REG(CFG_HWQ0_ADDR);
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REG_FIELD_SET(CFG_DBG_HWQ0_TYPE, tmp, 0); // 0:TDMA, 1:CSMA
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REG_FIELD_SET(CFG_DBG_HWQ0_CAP, tmp, 1); // CAP1 as default
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RGF_HWQ_WRITE_REG(CFG_HWQ0_ADDR, tmp);
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/* delete timeout for long pkt */
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RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_0_ADDR,0x0);
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RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_1_ADDR,0x0);
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RGF_TMR_WRITE_REG(CFG_TX_TIMEOUT_2_ADDR,0x0);
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RGF_TMR_WRITE_REG(CFG_PHY_TX_TIMEOUT_ADDR,0x0);
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/* not ack by hw */
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#if PHY_RX_ACK_DIS == 1
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tmp = RGF_RX_READ_REG(CFG_RESP_CTRL_ADDR);
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REG_FIELD_SET(CFG_HW_RESP_EN, tmp, 0);
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RGF_RX_WRITE_REG(CFG_RESP_CTRL_ADDR, tmp);
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#endif
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#if PHY_PPM_CAL_SUPPORT == 1
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/* disable intr */
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PHY_WRITE_REG(CFG_BB_INT_EN_0_ADDR, 0);
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PHY_WRITE_REG(CFG_BB_INT_EN_1_ADDR, 0);
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PHY_WRITE_REG(CFG_BB_INT_EN_2_ADDR, 0);
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PHY_WRITE_REG(CFG_BB_INT_EN_3_ADDR, 0);
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#endif
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/* disable ts sync */
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR,0);
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#if PHY_KUNLUN2_PLATFORM_SUPPORT == 1
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/* mac trig */
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tmp = RGF_MAC_READ_REG(CFG_MAC_TRX_START_ADDR);
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REG_FIELD_SET(CFG_MAC_TRX_START_NEED_TRIG, tmp, 0);
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REG_FIELD_SET(CFG_MAC_TRX_START_TRIG, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_MAC_TRX_START_ADDR, tmp);
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#endif
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}
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void platform_rx_pre_init()
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{
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/* change clk to 150M */
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clk_core_freq_set(CPU_FREQ_150M);
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/* alloc 1K size ram */
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os_mem_init((uint8_t *)0xfff000,0x1000);
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}
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uint32_t phy_get_pb_buf_ptr_from_mpdu(volatile tx_mpdu_start *mpdu)
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{
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return mpdu->pb_list->pb_buf_addr;
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}
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void mac_sts_get(iot_mac_sts_info_t *mac_sts)
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{
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/* get mac statistics */
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mac_sts->mac_rx_ring0_dbg_cnt = RGF_RX_READ_REG(CFG_RX_RING0_DBG_CNT_ADDR);
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mac_sts->mac_rx_fc_dbg_cnt = RGF_RX_READ_REG(CFG_RX_FC_DBG_CNT_ADDR);
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mac_sts->mac_rx_pkt_det_cnt = RGF_RX_READ_REG(CFG_RX_PKT_DETECTED_CNT_ADDR);
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/* clear cnt */
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RGF_RX_WRITE_REG(CFG_DBG_CNT_CLR_ADDR,0x1f);
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RGF_RX_WRITE_REG(CFG_RX_DBG_CNT_CLR_ADDR,0xf);
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}
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