kunlun/inc/hw/reg/riscv/15/sec_sys_rf.h

//-----------------------------------
#define CFG_IP_VERSION_ADDR 0x0000
#define MOD_MULTIPLIER_VERSION_OFFSET 0
#define MOD_MULTIPLIER_VERSION_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SEC_ENABLE_ADDR 0x0004
#define CONV_EB_OFFSET 7
#define CONV_EB_MASK 0x00000080
#define CHACHA_EB_OFFSET 6
#define CHACHA_EB_MASK 0x00000040
#define RANDOM_EB_OFFSET 5
#define RANDOM_EB_MASK 0x00000020
#define SHA2_EB_OFFSET 4
#define SHA2_EB_MASK 0x00000010
#define SM2_EB_OFFSET 3
#define SM2_EB_MASK 0x00000008
#define SM3_EB_OFFSET 2
#define SM3_EB_MASK 0x00000004
#define SM4_EB_OFFSET 1
#define SM4_EB_MASK 0x00000002
#define AES_EB_OFFSET 0
#define AES_EB_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_START_ADDR 0x0008
#define CONV_START_OFFSET 5
#define CONV_START_MASK 0x00000020
#define CHACHA_START_OFFSET 4
#define CHACHA_START_MASK 0x00000010
#define RANDOM_START_OFFSET 3
#define RANDOM_START_MASK 0x00000008
#define SM2_START_OFFSET 2
#define SM2_START_MASK 0x00000004
#define SM3_START_OFFSET 1
#define SM3_START_MASK 0x00000002
#define SM4_START_OFFSET 0
#define SM4_START_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_SOFT_RST_ADDR 0x000C
#define CONV_SOFT_RST_OFFSET 7
#define CONV_SOFT_RST_MASK 0x00000080
#define CHACHA_SOFT_RST_OFFSET 6
#define CHACHA_SOFT_RST_MASK 0x00000040
#define RANDOM_SOFT_RST_OFFSET 5
#define RANDOM_SOFT_RST_MASK 0x00000020
#define AES_SOFT_RST_OFFSET 4
#define AES_SOFT_RST_MASK 0x00000010
#define SM4_SOFT_RST_OFFSET 3
#define SM4_SOFT_RST_MASK 0x00000008
#define SHA2_SOFT_RST_OFFSET 2
#define SHA2_SOFT_RST_MASK 0x00000004
#define SM3_SOFT_RST_OFFSET 1
#define SM3_SOFT_RST_MASK 0x00000002
#define SM2_SOFT_RST_OFFSET 0
#define SM2_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_INT_CLR_ADDR 0x0010
#define CONV_INT_CLR_OFFSET 5
#define CONV_INT_CLR_MASK 0x00000020
#define CHACHA_INT_CLR_OFFSET 4
#define CHACHA_INT_CLR_MASK 0x00000010
#define RANDOM_INT_CLR_OFFSET 3
#define RANDOM_INT_CLR_MASK 0x00000008
#define SM2_INT_CLR_OFFSET 2
#define SM2_INT_CLR_MASK 0x00000004
#define SM3_INT_CLR_OFFSET 1
#define SM3_INT_CLR_MASK 0x00000002
#define SM4_INT_CLR_OFFSET 0
#define SM4_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_SM2_MOD_MULTIPLY_CTRL_ADDR 0x0014
#define MOD_STORE_SWH_OFFSET 8
#define MOD_STORE_SWH_MASK 0x00000100
#define ENCRYPTION_MOD_OFFSET 0
#define ENCRYPTION_MOD_MASK 0x000000FF

//-----------------------------------
#define CFG_SM2_M_DASH_ADDR 0x0018
#define M_DASH_OFFSET 0
#define M_DASH_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM3_SHA2_MODE_ADDR 0x001C
#define HASH_VALUE_FROM_MEM_OFFSET 3
#define HASH_VALUE_FROM_MEM_MASK 0x00000008
#define SM3_SHA2_MODE_OFFSET 2
#define SM3_SHA2_MODE_MASK 0x00000004
#define SHA2_MODE_OFFSET 0
#define SHA2_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_SM3_SHA2_SOURCE_ADDR_ADDR 0x0020
#define SM3_SHA2_SOURCE_ADDR_OFFSET 0
#define SM3_SHA2_SOURCE_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM3_SHA2_ENCRYPT_LEN_ADDR 0x0024
#define SM3_SHA2_DATA_LEN_OFFSET 0
#define SM3_SHA2_DATA_LEN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM4_AES_CONTROL_ADDR 0x0028
#define GCM_SW_IV_LEN_OFFSET 16
#define GCM_SW_IV_LEN_MASK 0x001F0000
#define GCM_SW_CTRL_OFFSET 13
#define GCM_SW_CTRL_MASK 0x0000E000
#define START_2ST_OFFSET 12
#define START_2ST_MASK 0x00001000
#define GCM_SW_AUTH_LEN_OFFSET 7
#define GCM_SW_AUTH_LEN_MASK 0x00000F80
#define CRYPTO_SEL_OFFSET 5
#define CRYPTO_SEL_MASK 0x00000060
#define ENCRY_MODE_OFFSET 3
#define ENCRY_MODE_MASK 0x00000018
#define ENCRY_DECRY_SEL_OFFSET 2
#define ENCRY_DECRY_SEL_MASK 0x00000004
#define KEY_MODE_OFFSET 0
#define KEY_MODE_MASK 0x00000003

//-----------------------------------
#define CFG_SM4_INPUT_START_ADDR_ADDR 0x002C
#define INPUT_START_ADDR_OFFSET 0
#define INPUT_START_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM4_INPUT_DATA_LENGTH_ADDR 0x0030
#define DATA_LENGTH_OFFSET 0
#define DATA_LENGTH_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM4_OUTPUT_START_ADDR_ADDR 0x0034
#define OUTPUT_START_ADDR_OFFSET 0
#define OUTPUT_START_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RANDOM_CONTROL_ADDR 0x0038
#define RANDOM_UPDATE_MARK_OFFSET 13
#define RANDOM_UPDATE_MARK_MASK 0x00002000
#define RANDOM_MAX_NUMBER_OFFSET 4
#define RANDOM_MAX_NUMBER_MASK 0x00001FF0
#define RANDOM_SAMPLE_WID_OFFSET 0
#define RANDOM_SAMPLE_WID_MASK 0x0000000F

//-----------------------------------
#define CFG_SM4_AES_CTR_RANDOM_ADDR 0x003C
#define CTR_RANDOM_OFFSET 0
#define CTR_RANDOM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SM4_AES_CTR_COUNTER_ADDR 0x0040
#define CTR_CNT_OFFSET 0
#define CTR_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SEC_INT_STATUS_ADDR 0x0044
#define CONV_INT_OFFSET 5
#define CONV_INT_MASK 0x00000020
#define CHACHA_INT_OFFSET 4
#define CHACHA_INT_MASK 0x00000010
#define RANDOM_INT_OFFSET 3
#define RANDOM_INT_MASK 0x00000008
#define SM2_INT_OFFSET 2
#define SM2_INT_MASK 0x00000004
#define SM3_INT_OFFSET 1
#define SM3_INT_MASK 0x00000002
#define SM4_INT_OFFSET 0
#define SM4_INT_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_ENDIAN_CONFIG_ADDR 0x0048
#define GCM_TAG_ENDIAN_SEL_OFFSET 9
#define GCM_TAG_ENDIAN_SEL_MASK 0x00000200
#define RANDOM_OUT_ENDIAN_SEL_OFFSET 8
#define RANDOM_OUT_ENDIAN_SEL_MASK 0x00000100
#define SM2_OUT_ENDIAN_SEL_OFFSET 7
#define SM2_OUT_ENDIAN_SEL_MASK 0x00000080
#define SM3_OUT_ENDIAN_SEL_OFFSET 6
#define SM3_OUT_ENDIAN_SEL_MASK 0x00000040
#define SM4_OUT_ENDIAN_SEL_OFFSET 5
#define SM4_OUT_ENDIAN_SEL_MASK 0x00000020
#define CHACHA_ENDIAN_SEL_OFFSET 4
#define CHACHA_ENDIAN_SEL_MASK 0x00000010
#define RANDOM_ENDIAN_SEL_OFFSET 3
#define RANDOM_ENDIAN_SEL_MASK 0x00000008
#define SM2_ENDIAN_SEL_OFFSET 2
#define SM2_ENDIAN_SEL_MASK 0x00000004
#define SM3_ENDIAN_SEL_OFFSET 1
#define SM3_ENDIAN_SEL_MASK 0x00000002
#define SM4_ENDIAN_SEL_OFFSET 0
#define SM4_ENDIAN_SEL_MASK 0x00000001

//-----------------------------------
#define CFG_SEC_MEM_CLOCK_FORCE_ADDR 0x004C
#define CHACHA_MEM_CLOCK_FORCE_OFFSET 4
#define CHACHA_MEM_CLOCK_FORCE_MASK 0x00000010
#define RANDOM_MEM_CLOCK_FORCE_OFFSET 3
#define RANDOM_MEM_CLOCK_FORCE_MASK 0x00000008
#define SM2_MEM_CLOCK_FORCE_OFFSET 2
#define SM2_MEM_CLOCK_FORCE_MASK 0x00000004
#define SM3_MEM_CLOCK_FORCE_OFFSET 1
#define SM3_MEM_CLOCK_FORCE_MASK 0x00000002
#define SM4_MEM_CLOCK_FORCE_OFFSET 0
#define SM4_MEM_CLOCK_FORCE_MASK 0x00000001

//-----------------------------------
#define CFG_RANDOM_NONCE_ADDR 0x0050
#define RANDOM_NONCE_OFFSET 0
#define RANDOM_NONCE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GCM_AUTH_LEN_ADDR 0x0054
#define GCM_AUTH_LEN_OFFSET 0
#define GCM_AUTH_LEN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GCM_AUTH_START_ADDR_ADDR 0x0058
#define GCM_AUTH_START_ADDR_OFFSET 0
#define GCM_AUTH_START_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GCM_IV_LEN_ADDR 0x005C
#define GCM_IV_LEN_OFFSET 0
#define GCM_IV_LEN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GCM_IV_START_ADDR_ADDR 0x0060
#define GCM_IV_START_ADDR_OFFSET 0
#define GCM_IV_START_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CONV_CONFIG_ADDR 0x0064
#define CONV_SIGNED_SWH_OFFSET 18
#define CONV_SIGNED_SWH_MASK 0x00040000
#define CONV_SHIFT_NUM_OFFSET 10
#define CONV_SHIFT_NUM_MASK 0x0003FC00
#define CONV_PROC_WID_OFFSET 2
#define CONV_PROC_WID_MASK 0x000003FC
#define CONV_RESERVE_OFFSET 1
#define CONV_RESERVE_MASK 0x00000002
#define CONV_MODE_OFFSET 0
#define CONV_MODE_MASK 0x00000001

//HW module read/write macro
#define SEC_SYS_RF_READ_REG(addr) SOC_READ_REG(SEC_SYS_RF_BASEADDR + addr)
#define SEC_SYS_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SEC_SYS_RF_BASEADDR + addr,value)