kunlun/inc/hw/reg/riscv2/15/phy_int.h

//phy_int_base
#define PHY_INT_RX_ERR_RCV_PB_OFFSET 31
#define PHY_INT_RX_ERR_RCV_PB_MASK 0x80000000
#define PHY_INT_RX_FC_RAW_RECEIVE_OFFSET 30
#define PHY_INT_RX_FC_RAW_RECEIVE_MASK 0x40000000
#define PHY_INT_RX_PPM_FIFO_OFFSET 29
#define PHY_INT_RX_PPM_FIFO_MASK 0x20000000
#define PHY_INT_RX_TD_PKT_DET_OFFSET 28
#define PHY_INT_RX_TD_PKT_DET_MASK 0x10000000
#define PHY_INT_RX_TD_AGC_TIMEOUT_OFFSET 27
#define PHY_INT_RX_TD_AGC_TIMEOUT_MASK 0x08000000
#define PHY_INT_RX_TD_AGC_DONE_OFFSET 26
#define PHY_INT_RX_TD_AGC_DONE_MASK 0x04000000
#define PHY_INT_RX_TD_AGC_RAMPUP_OFFSET 25
#define PHY_INT_RX_TD_AGC_RAMPUP_MASK 0x02000000
#define PHY_INT_RX_TD_AGC_DROP_OFFSET 24
#define PHY_INT_RX_TD_AGC_DROP_MASK 0x01000000
#define PHY_INT_RX_FD_GP_SOUND_OFFSET 23
#define PHY_INT_RX_FD_GP_SOUND_MASK 0x00800000
#define PHY_INT_RX_FD_PLD_FAIL_OFFSET 22
#define PHY_INT_RX_FD_PLD_FAIL_MASK 0x00400000
#define PHY_INT_RX_FD_PLD_OK_OFFSET 21
#define PHY_INT_RX_FD_PLD_OK_MASK 0x00200000
#define PHY_INT_RX_FD_PB_FAIL_OFFSET 20
#define PHY_INT_RX_FD_PB_FAIL_MASK 0x00100000
#define PHY_INT_RX_FD_PB_OK_OFFSET 19
#define PHY_INT_RX_FD_PB_OK_MASK 0x00080000
#define PHY_INT_RX_FD_FC_FAIL_OFFSET 18
#define PHY_INT_RX_FD_FC_FAIL_MASK 0x00040000
#define PHY_INT_RX_FD_FC_OK_OFFSET 17
#define PHY_INT_RX_FD_FC_OK_MASK 0x00020000
#define PHY_INT_RX_FD_CH_EST_DONE_OFFSET 16
#define PHY_INT_RX_FD_CH_EST_DONE_MASK 0x00010000
#define PHY_INT_WAIT_PARSE_TIME_OUT_OFFSET 15
#define PHY_INT_WAIT_PARSE_TIME_OUT_MASK 0x00008000
#define PHY_INT_RX_FD_OVERFLOW_OFFSET 14
#define PHY_INT_RX_FD_OVERFLOW_MASK 0x00004000
#define PHY_INT_LOOPBACK_DONE_OFFSET 13
#define PHY_INT_LOOPBACK_DONE_MASK 0x00002000
#define PHY_INT_TX_SW_FC_TIMEOUT_OFFSET 12
#define PHY_INT_TX_SW_FC_TIMEOUT_MASK 0x00001000
#define PHY_INT_DC_LARGE_OFFSET 11
#define PHY_INT_DC_LARGE_MASK 0x00000800
#define PHY_INT_TX_PPM_FIFO_OFFSET 10
#define PHY_INT_TX_PPM_FIFO_MASK 0x00000400
#define PHY_INT_LIC_OVR_STRESS_OFFSET 9
#define PHY_INT_LIC_OVR_STRESS_MASK 0x00000200
#define PHY_INT_TX_TD_SYMB_DONE_OFFSET 8
#define PHY_INT_TX_TD_SYMB_DONE_MASK 0x00000100
#define PHY_INT_PHY_TX_START_OFFSET 7
#define PHY_INT_PHY_TX_START_MASK 0x00000080
#define PHY_INT_TX_FD_INSERT_PREAM_DONE_OFFSET 6
#define PHY_INT_TX_FD_INSERT_PREAM_DONE_MASK 0x00000040
#define PHY_INT_TX_TD_FC_DONE_OFFSET 5
#define PHY_INT_TX_TD_FC_DONE_MASK 0x00000020
#define PHY_INT_TX_TD_PREAM_DONE_OFFSET 4
#define PHY_INT_TX_TD_PREAM_DONE_MASK 0x00000010
#define PHY_INT_TX_TD_START_OFFSET 3
#define PHY_INT_TX_TD_START_MASK 0x00000008
#define PHY_INT_TX_FD_TX_STUCK_OFFSET 2
#define PHY_INT_TX_FD_TX_STUCK_MASK 0x00000004
#define PHY_INT_TX_FD_TX_ABORT_OFFSET 1
#define PHY_INT_TX_FD_TX_ABORT_MASK 0x00000002
#define PHY_INT_TX_FD_TX_DONE_OFFSET 0
#define PHY_INT_TX_FD_TX_DONE_MASK 0x00000001

//phy_int_ext
#define PHY_INT_VIT_DONE_OFFSET 31
#define PHY_INT_VIT_DONE_MASK 0x80000000
#define PHY_INT_VIT_FAIL_OFFSET 30
#define PHY_INT_VIT_FAIL_MASK 0x40000000
#define PHY_INT_RX_FD_RATE0_FIND_PKT_OFFSET 29
#define PHY_INT_RX_FD_RATE0_FIND_PKT_MASK 0x20000000
#define PHY_INT_RX_FD_RATE1_FIND_PKT_OFFSET 28
#define PHY_INT_RX_FD_RATE1_FIND_PKT_MASK 0x10000000
#define PHY_INT_RX_FD_SYMB_SYNC_EN_OFFSET 27
#define PHY_INT_RX_FD_SYMB_SYNC_EN_MASK 0x08000000
#define PHY_INT_RX_FD_FIND_M_SYMB_OFFSET 26
#define PHY_INT_RX_FD_FIND_M_SYMB_MASK 0x04000000
#define PHY_INT_RX_INVALID_TONE_MAP_OFFSET 25
#define PHY_INT_RX_INVALID_TONE_MAP_MASK 0x02000000
#define PHY_INT_RX_FD_ALL_EQU_DONE_OFFSET 24
#define PHY_INT_RX_FD_ALL_EQU_DONE_MASK 0x01000000
#define PHY_INT_RX_FD_CH_EQU_DONE_OFFSET 23
#define PHY_INT_RX_FD_CH_EQU_DONE_MASK 0x00800000
#define PHY_INT_RX_FD_CH_EQU_START_OFFSET 22
#define PHY_INT_RX_FD_CH_EQU_START_MASK 0x00400000
#define PHY_INT_TX_TMAP_NOT_AVAIL_OFFSET 21
#define PHY_INT_TX_TMAP_NOT_AVAIL_MASK 0x00200000
#define PHY_INT_TX_INVALID_TONE_MAP_OFFSET 20
#define PHY_INT_TX_INVALID_TONE_MAP_MASK 0x00100000
#define PHY_INT_PHY_TX_PRS_OFFSET 19
#define PHY_INT_PHY_TX_PRS_MASK 0x00080000
#define PHY_INT_FD_IDLE_DONE_OFFSET 18
#define PHY_INT_FD_IDLE_DONE_MASK 0x00040000
#define PHY_INT_PREAM_FEC_DONE_OFFSET 17
#define PHY_INT_PREAM_FEC_DONE_MASK 0x00020000
#define PHY_INT_PREAM_FFT_DONE_OFFSET 16
#define PHY_INT_PREAM_FFT_DONE_MASK 0x00010000
#define PHY_INT_FLUSH_BUFFER_DONE_OFFSET 15
#define PHY_INT_FLUSH_BUFFER_DONE_MASK 0x00008000
#define PHY_INT_FC_FEC_DONE_OFFSET 14
#define PHY_INT_FC_FEC_DONE_MASK 0x00004000
#define PHY_INT_FC_FFT_DONE_OFFSET 13
#define PHY_INT_FC_FFT_DONE_MASK 0x00002000
#define PHY_INT_PLD_FEC_DONE_OFFSET 12
#define PHY_INT_PLD_FEC_DONE_MASK 0x00001000
#define PHY_INT_PLD_FFT_DONE_OFFSET 11
#define PHY_INT_PLD_FFT_DONE_MASK 0x00000800
#define PHY_INT_WAIT_DONE_DONE_OFFSET 10
#define PHY_INT_WAIT_DONE_DONE_MASK 0x00000400
#define PHY_INT_PRS_FFT_DONE_OFFSET 9
#define PHY_INT_PRS_FFT_DONE_MASK 0x00000200
#define PHY_INT_PRS_FEC_DONE_OFFSET 8
#define PHY_INT_PRS_FEC_DONE_MASK 0x00000100
#define PHY_INT_LONG_PREAM_FEC_DONE_OFFSET 7
#define PHY_INT_LONG_PREAM_FEC_DONE_MASK 0x00000080
#define PHY_INT_LONG_PREAM_FFT_DONE_OFFSET 6
#define PHY_INT_LONG_PREAM_FFT_DONE_MASK 0x00000040
#define PHY_INT_FC101_FEC_DONE_OFFSET 5
#define PHY_INT_FC101_FEC_DONE_MASK 0x00000020
#define PHY_INT_FC101_FFT_DONE_OFFSET 4
#define PHY_INT_FC101_FFT_DONE_MASK 0x00000010
#define PHY_INT_TX_TD_FC101_DONE_OFFSET 2
#define PHY_INT_TX_TD_FC101_DONE_MASK 0x00000004
#define PHY_INT_TX_TD_PLD_DONE_OFFSET 1
#define PHY_INT_TX_TD_PLD_DONE_MASK 0x00000002
#define PHY_INT_PREAM_NEGTIVE_START_OFFSET 0
#define PHY_INT_PREAM_NEGTIVE_START_MASK 0x00000001

//PHY_INT_BASE_4
#define PHY_INT_PHY_TX_OFFSET 7
#define PHY_INT_PHY_TX_MASK 0x00000080
#define PHY_INT_SOUND_SNR_DUMP_DONE_OFFSET 6
#define PHY_INT_SOUND_SNR_DUMP_DONE_MASK 0x00000040
#define PHY_INT_SNR_DUMP_DONE_OFFSET 5
#define PHY_INT_SNR_DUMP_DONE_MASK 0x00000020
#define PHY_INT_WAIT_TMAP_TIME_OUT_OFFSET 4
#define PHY_INT_WAIT_TMAP_TIME_OUT_MASK 0x00000010
#define PHY_INT_G3_TX_UNDERFLOW_OFFSET 3
#define PHY_INT_G3_TX_UNDERFLOW_MASK 0x00000008
#define PHY_INT_RX_FFT_DONE_OFFSET 2
#define PHY_INT_RX_FFT_DONE_MASK 0x00000004
#define PHY_INT_TX_FFT_DONE_OFFSET 1
#define PHY_INT_TX_FFT_DONE_MASK 0x00000002
#define PHY_INT_FFT_INIT_DONE_INT_OFFSET 0
#define PHY_INT_FFT_INIT_DONE_INT_MASK 0x00000001

//INT_PHY_TX
#define PHY_INT_FEC_TIMEOUT_CONFIG_OFFSET 10
#define PHY_INT_FEC_TIMEOUT_CONFIG_MASK 0x00000400
#define PHY_INT_FEC_TIMEOUT_FC101_OFFSET 9
#define PHY_INT_FEC_TIMEOUT_FC101_MASK 0x00000200
#define PHY_INT_FEC_TIMEOUT_FC_OFFSET 8
#define PHY_INT_FEC_TIMEOUT_FC_MASK 0x00000100
#define PHY_INT_FEC_TIMEOUT_FC_CRC_OFFSET 7
#define PHY_INT_FEC_TIMEOUT_FC_CRC_MASK 0x00000080
#define PHY_INT_FEC_TIMEOUT_PB_OFFSET 6
#define PHY_INT_FEC_TIMEOUT_PB_MASK 0x00000040
#define PHY_INT_FEC_TIMEOUT_PB_CRC_OFFSET 5
#define PHY_INT_FEC_TIMEOUT_PB_CRC_MASK 0x00000020
#define PHY_INT_TX_FD_TIMEOUT_PREAM_OFFSET 4
#define PHY_INT_TX_FD_TIMEOUT_PREAM_MASK 0x00000010
#define PHY_INT_TX_FD_TIMEOUT_FC_OFFSET 3
#define PHY_INT_TX_FD_TIMEOUT_FC_MASK 0x00000008
#define PHY_INT_TX_FD_TIMEOUT_FC101_OFFSET 2
#define PHY_INT_TX_FD_TIMEOUT_FC101_MASK 0x00000004
#define PHY_INT_TX_FD_TIMEOUT_PLD_OFFSET 1
#define PHY_INT_TX_FD_TIMEOUT_PLD_MASK 0x00000002
#define PHY_INT_TX_FD_TIMEOUT_IFFT_OFFSET 0
#define PHY_INT_TX_FD_TIMEOUT_IFFT_MASK 0x00000001