103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
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/****************************************************************************
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*
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* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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*
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* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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* be copied by any method or incorporated into another program without
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* the express written consent of Aerospace C.Power. This Information or any portion
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* thereof remains the property of Aerospace C.Power. The Information contained herein
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* is believed to be accurate and Aerospace C.Power assumes no responsibility or
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* liability for its use in any way and conveys no license or title under
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* any patent or copyright and makes no representation or warranty that this
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* Information is free from patent or copyright infringement.
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*
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* ****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "iot_irq.h"
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#include "iot_wdg.h"
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#include "os_mem.h"
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#include "efuse.h"
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#include "iot_system.h"
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#include "iot_io.h"
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#include "platform.h"
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#include "encoding.h"
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extern void def_trap_entry_2();
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extern void intc_handler(uint32_t cpu);
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cpu_state g_cpu1_state;
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static void exception_handler_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
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{
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/* save cpu1's crash state */
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g_cpu1_state.crash = 1;
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g_cpu1_state.mcause = mcause;
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g_cpu1_state.mepc = epc;
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g_cpu1_state.trap_frame = reg;
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while(1);
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}
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uintptr_t handle_trap_2(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
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{
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if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
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intc_handler(HAL_INTR_CPU_1);
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}else {
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exception_handler_2(mcause, epc, reg);
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}
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return epc;
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}
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void _init_2()
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{
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write_csr(mtvec, &def_trap_entry_2);
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clear_csr(mie, MIP_MEIP);
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clear_csr(mie, MIP_MTIP);
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iot_interrupt_init(HAL_INTR_CPU_1);
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set_csr(mie, MIP_MEIP);
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// Enable interrupts in general.
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set_csr(mstatus, MSTATUS_MIE);
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wdg_deinit(HAL_WDG_CPU_1);
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g_cpu1_state.flags = CPU_FLAG_RUNNING;
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}
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void _fini()
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{
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}
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void assert_failed( unsigned char *pucFile, unsigned long ulLine )
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{
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( void ) pucFile;
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( void ) ulLine;
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g_cpu1_state.assert_failed = 1;
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if (pucFile) {
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os_mem_cpy(g_cpu1_state.assert_info.file, pucFile, 32);
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} else {
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os_mem_set(g_cpu1_state.assert_info.file, 0, 32);
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}
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g_cpu1_state.assert_info.line = ulLine;
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/* do a breakpoint exception */
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asm volatile("ebreak");
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}
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void assert_failed_simple()
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{
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g_cpu1_state.assert_failed = 1;
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os_mem_set(g_cpu1_state.assert_info.file, 0, 32);
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g_cpu1_state.assert_info.line = 0;
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/* do a breakpoint exception */
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asm volatile("ebreak");
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}
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