kunlun/inc/hw/reg/riscv/15/hw_war.h

/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#ifndef _HW_WAR_H_
#define _HW_WAR_H_

#include "iot_config.h"

/* define which level would make SW ASSERT when abnormal HW behavior */
#define PLC_HW_ISSUE_ASSERT_ALL         0
#define PLC_HW_ISSUE_ASSERT_DEBUG       1
#define PLC_HW_ISSUE_ASSERT_CRITICAL    3
#define PLC_HW_ISSUE_ASSERT_BLOCK       5
#define PLC_HW_ISSUE_ASSERT_LEVEL       PLC_HW_ISSUE_ASSERT_DEBUG

/******************hw war macro******************/

#ifndef ENA_WAR_421_DEBUG
#define ENA_WAR_421_DEBUG               IOT_MP_SUPPORT
#endif

/* MAC HW overwrite WAR */
#define ENA_WAR_396                     1
#define ENA_WAR_396_DEBUG               1

/* sack war */
#define ENA_WAR_244                     IOT_MP_SUPPORT

/*rawdata mode write fl war*/
#define ENA_WAR_325                     IOT_MP_SUPPORT

/*spg tx ok always 1*/
#if SUPPORT_SOUTHERN_POWER_GRID
#define ENA_WAR_SPG_TX_OK               IOT_MP_SUPPORT
#define ENA_WAR_NSG_EXTMI               0
#else
#define ENA_WAR_SPG_TX_OK               0
#define ENA_WAR_NSG_EXTMI               0
#endif

/*TODO: ENA_WAR_SPG_TX_OK and ENA_WAR_NSG_EXTMI mutex.
 * need fix this bug.
 */
#if ENA_WAR_SPG_TX_OK && ENA_WAR_NSG_EXTMI
#error "spg tx ok war and spg extmi war can not both enable!"
#endif

#define ENA_SYNC_DIFF_CCO_PPM           (((PLC_SUPPORT_CCO_ROLE == 0) \
                                         || MAC_MM_SNIFFER_MODE) \
                                        && IOT_MP_SUPPORT)

/* KL1 war multi ppm tx rx */
#define ENA_SW_SYNC_PPM_WAR             (ENA_SYNC_DIFF_CCO_PPM)

/* tx ppm per pkt */
#define ENA_DBG_TX_PPM_PER_PKT          (ENA_SYNC_DIFF_CCO_PPM)

/* tx dbg pkt retry ppm */
#define ENA_DBG_PKT_TX_RETRY_PPM        (SUPPORT_SMART_GRID && \
                                        IOT_DEV_TEST_CCO_MODE && 0)

/* kl1 mac rx mpdu complete dsr disable bb rx ppm, phy isr set rx bbppm
 * 0   enable
 * 1   disable
 */
#define ENA_RX_BB_PPM                   1

/* nncco war */
#if PLC_SUPPORT_NEIGHBOR_NW_NEGO
#define ENA_WAR_NNCCO_FEAT              IOT_MP_SUPPORT
#else
#define ENA_WAR_NNCCO_FEAT              0
#endif

#ifndef ENA_WAR_440
#define ENA_WAR_440                     0
#endif

/* tx start war */
#ifndef ENA_MAC_TX_START_INT
#define ENA_MAC_TX_START_INT            IOT_MP_SUPPORT
#endif

/* war enable control macro */
#if (ENA_WAR_244 || ENA_WAR_NNCCO_FEAT || ENA_WAR_SPG_TX_OK || \
    ENA_MAC_TX_START_INT)
#define ENA_WAR_CTL                     1
#else
#define ENA_WAR_CTL                     0
#endif
//war for timeout tx abort
#define WAR_TIMEOUT_TX_ABORT            IOT_MP_SUPPORT
#define MAC_WAR_244_TIMESTAMPING        IOT_MP_SUPPORT

//war for ring re-enable
#define MAC_WAR_218                     (HW_PLATFORM >= HW_PLATFORM_FPGA)

/* war for rx desc not complete for the whole mpdu
 * SW pop buf from ring for wr idx update
 * and check the rx_pb_done, once it's set,
 * SW thought HW has complete the whole buf
 * but HW maybe complete when multi-pb case
 * the rx_mpdu_done may update after rx_pb_done
 * this would make SW think it's an error case
 * enable the following macro to force SW
 * wait first pb's attention desc to be rx_mpdu_done
 * set, if not, SW would keep waiting and hang
 */
#define MAC_RX_RING_WAIT_MPDU_DONE      0

/* kl1 rifs shares the same value
 * for tx and rx, we use a WAR to
 * make the rifs value be different
 * when tx and rx an uni-cast mpdu
 */
#define MAC_WAR_SPLIT_TX_RX_RIFS        IOT_MP_SUPPORT

/*enable hwretry bcast
 *hwretry and sw retry can not both enable
 */
#ifndef MAC_BCAST_HWRETRY_ENABLE
#define MAC_BCAST_HWRETRY_ENABLE        0
#endif

/* for WAR MAC HW overwrite issue */
#if ENA_WAR_396 //TODO: maybe only enable for CCO
#define MAC_HW_WAR_RESV_BYTES           (16 << 2)
#if (SUPPORT_SOUTHERN_POWER_GRID && PLC_SUPPORT_CCO_ROLE)
/* TODO: maybe spg sta also need to resv same as cco  */
#define MAC_HW_WAR_SPG_RESV_SHORT_BYTES (13 << 2)
#endif
#endif

#if !defined(MAC_HW_WAR_RESV_BYTES)
#define MAC_HW_WAR_RESV_BYTES           (0)
#endif

#if !defined(MAC_HW_WAR_SPG_RESV_SHORT_BYTES)
#define MAC_HW_WAR_SPG_RESV_SHORT_BYTES (0)
#endif

#ifndef DEBUG_NID_ERR
#define DEBUG_NID_ERR                   (IOT_MP_SUPPORT)
#endif

#ifndef WAR_SPUR_CHECK_FAIL_COLD_RESET
#define WAR_SPUR_CHECK_FAIL_COLD_RESET  0   //(IOT_MP_SUPPORT)
#endif

/* WAR for NTB update HW Bug */
#define ENA_WAR_728                     (IOT_MP_SUPPORT)

#ifndef WAR_BUGID757_EN
/* master and role is cco to debug */
#define WAR_BUGID757_EN                 (1)
#endif

#if DEBUG_HWQ_SHCED_HANG
#define WAR_HWQ_SHCED_HANG              0
#endif

/* SW SYNC NTB, low 32 bit overflow, high 32 bit not + 1*/
#ifndef ENA_WAR_911
#define ENA_WAR_911                     (1)
#endif

/* define high32bit ntb equal 1 */
#ifndef ENA_HIGH32_EQUAL_ONE
#define ENA_HIGH32_EQUAL_ONE            (!ENA_WAR_911)
#endif

/* war for low power mode */
#define WAR_FOR_LOW_POWER               0

#endif