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kunlun/dtest/dtest3/kl3_sadc_test/main.c

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2024-09-28 14:24:04 +08:00
/****************************************************************************
*
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
*
* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
* be copied by any method or incorporated into another program without
* the express written consent of Aerospace C.Power. This Information or any portion
* thereof remains the property of Aerospace C.Power. The Information contained herein
* is believed to be accurate and Aerospace C.Power assumes no responsibility or
* liability for its use in any way and conveys no license or title under
* any patent or copyright and makes no representation or warranty that this
* Information is free from patent or copyright infringement.
*
* ****************************************************************************/
#include "os_types.h"
#include "os_task.h"
#include "os_utils.h"
#include "hw_reg_api.h"
#include "apb_hw.h"
#include "apb.h"
/* common includes */
#include "iot_io.h"
#include "iot_bitops.h"
#include "iot_pkt_api.h"
/* debug includes*/
#include "dbg_io.h"
#include "iot_errno_api.h"
#include "uart.h"
#include "iot_clock.h"
#include "iot_config.h"
#include "iot_uart_api.h"
#include "iot_errno_api.h"
#include "iot_adc_api.h"
#include "ahb.h"
#include "rtc.h"
#include "chip_reg_base.h"
#include "hw_reg_api.h"
#include "iot_irq.h"
#include "iot_wdg.h"
#include "sar_adc_reg.h"
#include "sar_adc_reg_s.h"
#include "sadc.h"
#include "sadc_hw.h"
#pragma GCC push_options
#pragma GCC optimize("O0")
#define TEST_SADC_INT_LEN 100
static uint32_t test_int_sadc_data[TEST_SADC_INT_LEN];
static uint32_t test_int_sadc_cnt;
static uint32_t test_sadc_port;
static volatile sar_adc_reg_t *sadc_bases[SADC_HW_DEV_NUM] = {
(volatile sar_adc_reg_t *)SADC_BASEADDR,
(volatile sar_adc_reg_t *)TPID_BASEADDR,
};
void sadc_set_adc_full_int_eb(uint8_t port, bool_t eb)
{
WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc_full_int_ena, eb);
}
void sadc_set_adc_valid_int_eb(uint8_t port, uint8_t ch, bool_t eb)
{
switch (ch) {
case 0: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc0_valid_int_ena, eb);break;
case 1: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc1_valid_int_ena, eb);break;
case 2: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc2_valid_int_ena, eb);break;
case 3: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc3_valid_int_ena, eb);break;
case 4: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc4_valid_int_ena, eb);break;
case 5: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc5_valid_int_ena, eb);break;
case 6: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc6_valid_int_ena, eb);break;
case 7: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc7_valid_int_ena, eb);break;
case 8: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc8_valid_int_ena, eb);break;
case 9: WR_REG_FIELD(sadc_bases[port]->adc_int_ena, adc9_valid_int_ena, eb);break;
default:break;
}
}
bool_t sadc_get_adc_valid_int_st(uint8_t port, uint8_t ch)
{
bool_t res = false;
switch (ch) {
case 0: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc0_valid_int_st) ? true : false;break;
case 1: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc1_valid_int_st) ? true : false;break;
case 2: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc2_valid_int_st) ? true : false;break;
case 3: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc3_valid_int_st) ? true : false;break;
case 4: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc4_valid_int_st) ? true : false;break;
case 5: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc5_valid_int_st) ? true : false;break;
case 6: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc6_valid_int_st) ? true : false;break;
case 7: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc7_valid_int_st) ? true : false;break;
case 8: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc8_valid_int_st) ? true : false;break;
case 9: res = RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc9_valid_int_st) ? true : false;break;
default:break;
}
return res;
}
void sadc_clr_adc_int(uint8_t port)
{
WR_REG_FIELD(sadc_bases[port]->adc_int_clr, adc_full_int_clr, 1);
// for (volatile uint32_t i = 0; i < 1000; i++);
WR_REG_FIELD(sadc_bases[port]->adc_int_clr, adc_full_int_clr, 0);
}
uint32_t sadc_get_adc_int_st(uint8_t port)
{
return RE_REG_FIELD(sadc_bases[port]->adc_int_st, adc_full_int_st);
}
uint32_t sadc_get_adc_int_raw(uint8_t port)
{
return RE_REG_FIELD(sadc_bases[port]->adc_int_raw, adc_full_int_raw);
}
int32_t test_sadc_get_rdata(uint32_t port, uint32_t phs)
{
uint32_t res;
uint32_t ch = 0;
switch (ch) {
case 0:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc0_rdata, adc0_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc0_rdata, adc0_phase_clr, 1);
break;
case 1:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc1_rdata, adc1_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc1_rdata, adc1_phase_clr, 1);
break;
case 2:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc2_rdata, adc2_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc2_rdata, adc2_phase_clr, 1);
break;
case 3:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc3_rdata, adc3_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc3_rdata, adc3_phase_clr, 1);
break;
case 4:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc4_rdata, adc4_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc4_rdata, adc4_phase_clr, 1);
break;
case 5:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc5_rdata, adc5_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc5_rdata, adc5_phase_clr, 1);
break;
case 6:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc6_rdata, adc6_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc6_rdata, adc6_phase_clr, 1);
break;
case 7:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc7_rdata, adc7_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc7_rdata, adc7_phase_clr, 1);
break;
case 8:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc8_rdata, adc8_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc8_rdata, adc8_phase_clr, 1);
break;
case 9:
res = RE_REG_FIELD(sadc_bases[port]->sar_adc9_rdata, adc9_data);
WR_REG_FIELD(sadc_bases[port]->sar_adc9_rdata, adc9_phase_clr, 1);
break;
default:break;
}
return res;
}
static uint32_t test_sadc_irq_handler(uint32_t vector, iot_addrword_t data)
{
uint32_t ch = data;
if (sadc_get_adc_valid_int_st(test_sadc_port, ch)) {
if (test_int_sadc_cnt < TEST_SADC_INT_LEN - 1) {
test_int_sadc_data[test_int_sadc_cnt] = (uint32_t)test_sadc_get_rdata(test_sadc_port, ch);;
} else if (test_int_sadc_cnt == TEST_SADC_INT_LEN - 1) {
test_int_sadc_data[test_int_sadc_cnt] = (uint32_t)test_sadc_get_rdata(test_sadc_port, ch);;
/* disable data valid interrupt */
sadc_set_adc_valid_int_eb(test_sadc_port, ch, 0);
}
test_int_sadc_cnt++;
}
return 0;
}
static void sadc_data_dump_average(char *str, uint32_t *buf, uint32_t len)
{
iot_printf("[%s SADC_DATA_DUMP]len=%d\n", str, len);
for (uint32_t i = 0; i < len; i++) {
iot_printf("[%d]:phase=%d,data=%d\n", i,
0xF & (buf[i] >> 28),
0x3FF & buf[i]);
}
}
sar_adc_reg_t *test_g_sar_adc_reg;
int main(void)
{
uint8_t channel = 1;
uint8_t err_num_volt = 0;
iot_irq_t test_sadc_irq_h;
int test_poll_cnt = 0;
float temp_value;
uint8_t adc_ch[8] = {ADC_CHANNEL0, ADC_CHANNEL1, ADC_CHANNEL2,
ADC_CHANNEL3, ADC_CHANNEL4, ADC_CHANNEL5, ADC_CHANNEL6, ADC_CHANNEL7};
wdg_deinit(HAL_WDG_CPU_0);
wdg_deinit(HAL_WDG_CPU_1);
wdg_deinit(HAL_WDG_CPU_2);
dbg_uart_init();
iot_printf("sadc test\n");
sadc_init(ANA_SADC0, NULL);
if (0) { /* sadc interrupt test */
test_sadc_port = ANA_SADC0;
test_sadc_irq_h = iot_interrupt_create(HAL_VECTOR_SADC,
HAL_INTR_PRI_6, (iot_addrword_t)channel, test_sadc_irq_handler);
iot_interrupt_attach(test_sadc_irq_h);
iot_interrupt_unmask(test_sadc_irq_h);
/* enable data valid interrupt */
sadc_set_adc_valid_int_eb(test_sadc_port, channel, 1);
/* wait for sampling to complete */
while (test_int_sadc_cnt < TEST_SADC_INT_LEN);
sadc_data_dump_average("INT-P0", test_int_sadc_data, TEST_SADC_INT_LEN);
}
while (1) {
test_g_sar_adc_reg = (sar_adc_reg_t*)(SADC_BASEADDR);
//if (0) {
for (int ch_idx = 0; ch_idx < 6; ch_idx++) {
channel = adc_ch[ch_idx];
int adc_volt = sadc_poll_volt_start_real(channel, ADC_GAIN_3V,
&err_num_volt);
if (err_num_volt != 0) {
iot_printf("adc channel %d data is invaild!\n", channel);
} else {
iot_printf("%d,%d ", ch_idx, adc_volt);
}
}
//} else {
sadc_temperature_val_get_raw(&temp_value);
iot_printf("temp=%f ", temp_value);
//}
for (volatile uint32_t i = 0; i < 1000; i++);
iot_printf("\n");
/* test sadc ahb disable */
if (0 && test_poll_cnt++ > 20) {
iot_printf("stop sadc\r\n");
apb_disable(APB_SADC);
}
}
return 0;
}
#pragma GCC pop_options