418 lines
11 KiB
C
418 lines
11 KiB
C
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/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "iot_bitops.h"
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#include "dtest_printf.h"
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#include "cpu.h"
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#include "ahb.h"
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#if HW_PLATFORM > HW_PLATFORM_SIMU
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#include "dbg_io.h"
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#endif
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#include "watchdog.h"
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#include "chip_reg_base.h"
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#include "ahb_rf_s.h"
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#include "uart.h"
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#include "strformat.h"
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#include "uart_e.h"
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extern iot_wdg_info g_wdg_info[3];
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extern iot_wdg_info g_wdg_timeout;
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extern int g_feed_dog[3];
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extern void _core_start(void);
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extern void _start(void);
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typedef struct _wdg_typedef
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{
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uint32_t RVER1;
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struct
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{
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uint32_t rver1 : 7;
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uint32_t fullrst_cnt_en : 1;
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uint32_t rver2 : 7;
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uint32_t cpurst_cnt_en : 1;
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uint32_t rver3 : 7;
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uint32_t timeout_cnt_en : 1;
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uint32_t rver4 : 7;
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uint32_t cnt_en : 1;
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}CTL0;
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struct
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{
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uint32_t rver1 : 7;
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uint32_t fullrst_inter_en : 1;
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uint32_t rver2 : 7;
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uint32_t cpurst_inter_en : 1;
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uint32_t rver3 : 7;
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uint32_t timeout_inter_en : 1;
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uint32_t rver4 : 7;
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uint32_t inter_en : 1;
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}CTL1;
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uint32_t CTL2;
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uint32_t CNT;
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uint32_t CMP;
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struct
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{
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uint32_t rver1 : 8;
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uint32_t fullrst_cnt : 8;
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uint32_t cputrst_cnt : 8;
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uint32_t timeout_cnt : 8;
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}CNTS;
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struct
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{
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uint32_t rver1 : 8;
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uint32_t fullrst_cmp : 8;
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uint32_t cputrst_cmp : 8;
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uint32_t timeout_cmp : 8;
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}CMPS;
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struct
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{
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uint32_t rver1 : 24;
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uint32_t cpurst_width : 8;
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}CPURST_WIDTH;
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uint32_t RVER2[0x60];
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uint32_t PROTECT_CODE;
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}wdg_typdef;
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typedef enum
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{
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TEST_MODE_CPURST = 0,
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TEST_MODE_FULLRST,
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}TEST_MODE;
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//wdg_typdef *WDG
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static volatile ahb_lite_reg_t *ahb_base =
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(volatile ahb_lite_reg_t *)AHB_REG_LITE_BASEADDR;
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extern struct uart_ctrl uart_e_ctrl;
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#define my_g_uart_ctrl uart_e_ctrl
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void delay_sometime(void) {
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uint32_t loop;
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loop = 0;
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while(loop++ < 1000000) __asm volatile ("nop\n");
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}
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void core_print_regs(UART_PORT port, char *buf, int len, uint32_t cur_cpu) {
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uint32_t pc;
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uint32_t rst_flag;
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int str_len;
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uint32_t *reg = (uint32_t *)WDG0_REG_BASEADDR ;
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switch(cur_cpu) {
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case 0:
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pc = ahb_base->cpu0_start_pc.w;
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reg = (uint32_t *)WDG0_REG_BASEADDR ;
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break;
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case 1:
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pc = ahb_base->cpu1_start_pc.w;
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reg = (uint32_t *)WDG1_REG_BASEADDR ;
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break;
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case 2:
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pc = ahb_base->cpu2_start_pc.w;
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reg = (uint32_t *)WDG2_REG_BASEADDR ;
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break;
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}
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rst_flag = *( (uint32_t *)(0x40000000 + 0x008C) );
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str_len = iot_snprintf(buf, len, "cpu:%d,ctl0:%08x,ctl1:%08x,cnt:%08x,\
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cmp:%08x,cnts:%08x,cmps:%08x,width:%08x,pc=%08x,rst_flag=%08x\r\n",
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cur_cpu, *(reg + 1),*(reg + 2), *(reg + 4), *(reg + 5), *(reg+6), *(reg+7),
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*(reg+8), pc , rst_flag);
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my_g_uart_ctrl.puts(port, (uint8_t*)buf, str_len);
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}
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/*
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port:输出日志的串口编号
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pin_num:对应串口的txd引脚编号
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buf:输出日志时用的缓存地址
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buf_len:缓存大小
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mode :测试cpurst还是fullrst
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*/
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void core_wdg_test_loop(UART_PORT port, int pin_num, char *buf, int buf_len,
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TEST_MODE mode) {
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uint32_t cnt = 0;
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uint32_t cur_cpu = cpu_get_mhartid();
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// UART0 init
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my_g_uart_ctrl.init(port);
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my_g_uart_ctrl.config(port, 115200, UART_DATA_8_BITS, UART_STOP_BITS_1,
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UART_PARITY_DISABLE);
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iot_uart_set_pin(port, 0xff, pin_num);
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my_g_uart_ctrl.puts(port, (uint8_t*)"00000\r\n", 7);
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int str_len ;
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// print start
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str_len = iot_snprintf(buf, buf_len, "CPU %d : Start 0000!!!\r\n", cur_cpu);
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my_g_uart_ctrl.puts(port, (uint8_t*)buf, str_len);
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delay_sometime();
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//wdg init
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core_print_regs(port, buf, buf_len, cur_cpu);
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wdg_deinit(cur_cpu);
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wdg_init(cur_cpu);
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if (TEST_MODE_CPURST == mode) {
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wdg_set_cmp(cur_cpu, 50000);//SET_WDG_INTC_CMP);
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wdg_set_timeout_cmp(cur_cpu, 15);//SET_WDG_TIMEOUT_CMP);
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wdg_set_cpurst_cmp(cur_cpu, 5);//SET_WDG_CPURST_CMP );
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wdg_set_fullrst_cmp(cur_cpu, 10);//SET_WDG_FULLRST_CMP);
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} else if (TEST_MODE_FULLRST == mode) {
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wdg_set_cmp(cur_cpu, 50000);//SET_WDG_INTC_CMP);
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wdg_set_timeout_cmp(cur_cpu, 15);//SET_WDG_TIMEOUT_CMP);
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wdg_set_cpurst_cmp(cur_cpu, 10);//SET_WDG_CPURST_CMP );
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wdg_set_fullrst_cmp(cur_cpu, 5);//SET_WDG_FULLRST_CMP);
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} else {
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}
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while(1) {
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//delay_sometime();
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//core_print_regs(port, buf, buf_len, cur_cpu);
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if (g_feed_dog[cur_cpu] == 1 && cnt < 5) {
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str_len = iot_snprintf(buf, buf_len,
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"cnt %d, feed dog cpu%d\r\n", cnt, cur_cpu);
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my_g_uart_ctrl.puts(port, (uint8_t*)buf, str_len);
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wdg_feed_dog(cur_cpu);
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iot_interrupt_unmask(g_wdg_info[cur_cpu].handle);
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g_feed_dog[cur_cpu] = 0;
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cnt++;
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}
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}
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}
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void core_working_loop(UART_PORT port, int pin_num, char *buf, int buf_len) {
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uint32_t cur_cpu = cpu_get_mhartid();
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// UART init
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my_g_uart_ctrl.init(port);
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my_g_uart_ctrl.config(port, 115200, UART_DATA_8_BITS, UART_STOP_BITS_1,
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UART_PARITY_DISABLE);
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iot_uart_set_pin(port, 0xff, pin_num);
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int str_len ;
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int inc = 0;
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while(1) {
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str_len = iot_snprintf(buf, buf_len, "CPU %d : %d\r\n", cur_cpu, inc);
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my_g_uart_ctrl.puts(port, (uint8_t*)buf, str_len);
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inc ++;
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if(inc > 10000)
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inc = 0;
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delay_sometime();
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}
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}
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/*
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WDG_TEST_FUNC 可定义如下些值
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0:仅core0 看门狗cpurst
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1:core0 rst core1 core2 正常运行
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2:core1 rst core0 core2 正常运行
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3:core2 rst core0 core1 正常运行
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4:core0 rst core1 rst core2 rst
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*/
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#define WDG_TEST_FUNC 1
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/*
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TEST_MODE_CPURST
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TEST_MODE_FULLRST
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*/
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/*
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由于当前时在FPGA上跑的，fullrst 后会对start pc复位成 20000
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而当前这个地方没有东西，复位过去没法执行，也就是当前没法测
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fullrst
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由于core_start.S中调用了_init 函数，它会重新初始化中断
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导致core2 的cpurst不再响应，若要测试它请将core_start.s中
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的
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li t0, 2
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改成
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li t0, 1
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*/
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#define CUR_TEST_MODE TEST_MODE_CPURST
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#define UART0_GPIO 6
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#define UART1_GPIO 8
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#define UART2_GPIO 36
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int main(void) {
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uint32_t cur_cpu = cpu_get_mhartid();
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dbg_uart_init();
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// 26 27 28
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#if (WDG_TEST_FUNC == 0)
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static char buf[500];
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if (0 == cur_cpu) {
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ahb_core0_set_start((uint32_t) _start);
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} else if (1 == cur_cpu) {
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ahb_core1_set_start((uint32_t) _start);
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} else {
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ahb_core2_set_start((uint32_t) _start);
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}
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core_wdg_test_loop(UART_PT1, UART1_GPIO, buf, sizeof(buf), CUR_TEST_MODE);
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#elif (WDG_TEST_FUNC == 1) //
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if (0 == cur_cpu) {
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static char buf0[500];
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//core1没有启动时才启动，否则core1就相当于重启了，等同于被复位
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if ((ahb_base->ahb_reg0.w & (1 << AHB_RV5_CORE1_RST))) {
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ahb_core1_set_start((uint32_t) _core_start);
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ahb_core1_enable();
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ahb_core1_reset();
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}
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ahb_core0_set_start((uint32_t) _start);
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core_wdg_test_loop(UART_PT1, UART1_GPIO, buf0, sizeof(buf0), CUR_TEST_MODE);
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} else if(1 == cur_cpu) {
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static char buf[500];
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ahb_core2_set_start((uint32_t) _core_start);
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ahb_core2_enable();
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ahb_core2_reset();
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while(1) {
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core_working_loop(UART_PT0, UART0_GPIO, buf, sizeof(buf));
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}
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} else {
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static char buf2[500];
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while(1) {
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core_working_loop(UART_PT2, UART2_GPIO, buf2, sizeof(buf2) );
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}
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}
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#elif (WDG_TEST_FUNC == 2)
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if (0 == cur_cpu) {
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static char buf0[500];
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ahb_core1_set_start((uint32_t) _core_start);
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ahb_core1_enable();
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ahb_core1_reset();
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while(1) {
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core_working_loop(UART_PT0, UART0_GPIO, buf0, sizeof(buf0));
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}
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} else if(1 == cur_cpu) {
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static char buf[500];
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if ((ahb_base->ahb_reg0.w & (1 << AHB_RV5_CORE2_RST))) {
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ahb_core2_set_start((uint32_t) _core_start);
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ahb_core2_enable();
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ahb_core2_reset();
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}
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core_wdg_test_loop(UART_PT1, UART1_GPIO, buf, sizeof(buf), CUR_TEST_MODE);
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|
}else {
|
|||
|
|
static char buf2[500];
|
|||
|
|
while(1) {
|
|||
|
|
core_working_loop(UART_PT2, UART2_GPIO, buf2, sizeof(buf2) );
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
#elif (WDG_TEST_FUNC == 3)
|
|||
|
|
if (0 == cur_cpu) {
|
|||
|
|
static char buf0[500];
|
|||
|
|
ahb_core1_set_start((uint32_t) _core_start);
|
|||
|
|
ahb_core1_enable();
|
|||
|
|
ahb_core1_reset();
|
|||
|
|
|
|||
|
|
while(1) {
|
|||
|
|
core_working_loop(UART_PT0, UART0_GPIO, buf0, sizeof(buf0));
|
|||
|
|
}
|
|||
|
|
} else if(1 == cur_cpu) {
|
|||
|
|
static char buf[500];
|
|||
|
|
|
|||
|
|
ahb_core2_set_start((uint32_t) _core_start);
|
|||
|
|
|
|||
|
|
ahb_core2_enable();
|
|||
|
|
ahb_core2_reset();
|
|||
|
|
|
|||
|
|
while(1) {
|
|||
|
|
core_working_loop(UART_PT2, UART2_GPIO, buf, sizeof(buf));
|
|||
|
|
}
|
|||
|
|
} else {
|
|||
|
|
static char buf2[500];
|
|||
|
|
core_wdg_test_loop(UART_PT1, UART1_GPIO, buf2, sizeof(buf2), CUR_TEST_MODE);
|
|||
|
|
}
|
|||
|
|
#elif (WDG_TEST_FUNC == 4)
|
|||
|
|
iot_interrupt_init();
|
|||
|
|
if (0 == cur_cpu) {
|
|||
|
|
static char buf0[500];
|
|||
|
|
ahb_core0_set_start((uint32_t) _start);
|
|||
|
|
if ((ahb_base->ahb_reg0.w & (1 << AHB_RV5_CORE1_RST))) {
|
|||
|
|
ahb_core1_set_start((uint32_t) _core_start);
|
|||
|
|
ahb_core1_enable();
|
|||
|
|
ahb_core1_reset();
|
|||
|
|
}
|
|||
|
|
while(1) {
|
|||
|
|
|
|||
|
|
core_wdg_test_loop(UART_PT0, UART0_GPIO, buf0, sizeof(buf0), CUR_TEST_MODE);
|
|||
|
|
}
|
|||
|
|
} else if(1 == cur_cpu) {
|
|||
|
|
static char buf[500];
|
|||
|
|
if((ahb_base->ahb_reg0.w & (1 << AHB_RV5_CORE2_RST))) {
|
|||
|
|
ahb_core2_set_start((uint32_t) _core_start);
|
|||
|
|
ahb_core2_enable();
|
|||
|
|
ahb_core2_reset();
|
|||
|
|
}
|
|||
|
|
while(1) {
|
|||
|
|
core_wdg_test_loop(UART_PT2, UART2_GPIO, buf, sizeof(buf), CUR_TEST_MODE);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
else {
|
|||
|
|
static char buf2[500];
|
|||
|
|
core_wdg_test_loop(UART_PT1, UART1_GPIO, buf2, sizeof(buf2), CUR_TEST_MODE);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#else
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
#endif
|
|||
|
|
while(1) {
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
|