kunlun/inc/hw/reg/riscv/13/ahb_rf.h

//-----------------------------------
#define CFG_AHB_RVER_ADDR 0x0000
#define AHB_RF_VER_OFFSET 0
#define AHB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_AHB_REG0_ADDR 0x0004
#define SW_DMA1_SOFT_RST_OFFSET 25
#define SW_DMA1_SOFT_RST_MASK 0x02000000
#define SW_DMA0_SOFT_RST_OFFSET 24
#define SW_DMA0_SOFT_RST_MASK 0x01000000
#define PHY_ANA_SOFT_RST_OFFSET 23
#define PHY_ANA_SOFT_RST_MASK 0x00800000
#define PHY_REG_SOFT_RST_OFFSET 22
#define PHY_REG_SOFT_RST_MASK 0x00400000
#define PHY_SOFT_RST_OFFSET 21
#define PHY_SOFT_RST_MASK 0x00200000
#define MAC_REG_SOFT_RST_OFFSET 20
#define MAC_REG_SOFT_RST_MASK 0x00100000
#define PERI_SYS_SOFT_RST_OFFSET 19
#define PERI_SYS_SOFT_RST_MASK 0x00080000
#define AHB_SYS_SOFT_RST_OFFSET 18
#define AHB_SYS_SOFT_RST_MASK 0x00040000
#define RV5_CORE1_SOFT_RST_P_OFFSET 17
#define RV5_CORE1_SOFT_RST_P_MASK 0x00020000
#define RV5_CORE0_SOFT_RST_P_OFFSET 16
#define RV5_CORE0_SOFT_RST_P_MASK 0x00010000
#define SEC_SOFT_RST_OFFSET 6
#define SEC_SOFT_RST_MASK 0x00000040
#define GMAC_SOFT_RST_OFFSET 5
#define GMAC_SOFT_RST_MASK 0x00000020
#define DCACHE_SOFT_RST_OFFSET 4
#define DCACHE_SOFT_RST_MASK 0x00000010
#define ICACHE_SOFT_RST_OFFSET 3
#define ICACHE_SOFT_RST_MASK 0x00000008
#define EMC_SOFT_RST_OFFSET 2
#define EMC_SOFT_RST_MASK 0x00000004
#define ADA_SOFT_RST_OFFSET 1
#define ADA_SOFT_RST_MASK 0x00000002
#define MAC_SOFT_RST_OFFSET 0
#define MAC_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_AHB_REG1_ADDR 0x0008
#define SW_DMA1_EB_OFFSET 25
#define SW_DMA1_EB_MASK 0x02000000
#define SW_DMA0_EB_OFFSET 24
#define SW_DMA0_EB_MASK 0x01000000
#define PHY_EB_OFFSET 20
#define PHY_EB_MASK 0x00100000
#define PERI_SYS_EB_OFFSET 19
#define PERI_SYS_EB_MASK 0x00080000
#define AHB_SYS_ENA_OFFSET 18
#define AHB_SYS_ENA_MASK 0x00040000
#define RV5_CORE1_ENA_OFFSET 17
#define RV5_CORE1_ENA_MASK 0x00020000
#define RV5_CORE0_ENA_OFFSET 16
#define RV5_CORE0_ENA_MASK 0x00010000
#define SEC_EB_OFFSET 6
#define SEC_EB_MASK 0x00000040
#define GMAC_EB_OFFSET 5
#define GMAC_EB_MASK 0x00000020
#define DCACHE_EB_OFFSET 4
#define DCACHE_EB_MASK 0x00000010
#define ICACHE_EB_OFFSET 3
#define ICACHE_EB_MASK 0x00000008
#define EMC_EB_OFFSET 2
#define EMC_EB_MASK 0x00000004
#define ADA_EB_OFFSET 1
#define ADA_EB_MASK 0x00000002
#define MAC_EB_OFFSET 0
#define MAC_EB_MASK 0x00000001

//-----------------------------------
#define CFG_AHB_CTR0_ADDR 0x000c
#define DCACHE_HIT_ERR_OFFSET 18
#define DCACHE_HIT_ERR_MASK 0x00040000
#define ICACHE_HIT_ERR_OFFSET 17
#define ICACHE_HIT_ERR_MASK 0x00020000
#define DCACHE_MODE_OFFSET 16
#define DCACHE_MODE_MASK 0x00010000
#define DCACHE_FSM_ST_OFFSET 12
#define DCACHE_FSM_ST_MASK 0x0000F000
#define ICACHE_FSM_ST_OFFSET 8
#define ICACHE_FSM_ST_MASK 0x00000F00
#define DCACHE_CLEAR_DONE_OFFSET 7
#define DCACHE_CLEAR_DONE_MASK 0x00000080
#define ICACHE_CLEAR_DONE_OFFSET 6
#define ICACHE_CLEAR_DONE_MASK 0x00000040
#define DCACHE_FLUSH_DONE_OFFSET 5
#define DCACHE_FLUSH_DONE_MASK 0x00000020
#define ICACHE_FLUSH_DONE_OFFSET 4
#define ICACHE_FLUSH_DONE_MASK 0x00000010
#define DCACHE_CLEAR_ENA_OFFSET 3
#define DCACHE_CLEAR_ENA_MASK 0x00000008
#define ICACHE_CLEAR_ENA_OFFSET 2
#define ICACHE_CLEAR_ENA_MASK 0x00000004
#define DCACHE_FLUSH_ENA_OFFSET 1
#define DCACHE_FLUSH_ENA_MASK 0x00000002
#define ICACHE_FLUSH_ENA_OFFSET 0
#define ICACHE_FLUSH_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_DBG_CTR_ADDR 0x0010
#define BB_ADC_SCALE_SEL_OFFSET 8
#define BB_ADC_SCALE_SEL_MASK 0x00000F00
#define BB_DAC_SCALE_SEL_OFFSET 2
#define BB_DAC_SCALE_SEL_MASK 0x0000003C

//-----------------------------------
#define CFG_CLK_CFG0_ADDR 0x0014
#define CLK_SPI_INF_DIV_OFFSET 0
#define CLK_SPI_INF_DIV_MASK 0x00000003

//-----------------------------------
#define CFG_GMAC_REG1_ADDR 0x0018
#define GMAC_SBD_FLOWCTRL_OFFSET 13
#define GMAC_SBD_FLOWCTRL_MASK 0x00002000
#define GMAC_PTP_AUX_TS_TRIG_OFFSET 12
#define GMAC_PTP_AUX_TS_TRIG_MASK 0x00001000
#define GMAC_CORE_PHY_ADDR_OFFSET 8
#define GMAC_CORE_PHY_ADDR_MASK 0x00000F00
#define GMAC_PHY_INTF_SEL_OFFSET 0
#define GMAC_PHY_INTF_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_GMAC_REG2_ADDR 0x001c
#define GMAC_PTP_TIMESTMAP_L_OFFSET 0
#define GMAC_PTP_TIMESTMAP_L_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_GMAC_REG3_ADDR 0x0020
#define GMAC_PTP_TIMESTMAP_H_OFFSET 0
#define GMAC_PTP_TIMESTMAP_H_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CACHE_MON_CFG0_ADDR 0x0024
#define ICACHE_WR_MON_ENA_OFFSET 3
#define ICACHE_WR_MON_ENA_MASK 0x00000008
#define DCACHE_WR_MON_ENA_OFFSET 2
#define DCACHE_WR_MON_ENA_MASK 0x00000004
#define DCACHE_WR_MON_FLAG_OFFSET 1
#define DCACHE_WR_MON_FLAG_MASK 0x00000002
#define ICACHE_WR_MON_FLAG_OFFSET 0
#define ICACHE_WR_MON_FLAG_MASK 0x00000001

//-----------------------------------
#define CFG_ICACHE_MADDR_ADDR 0x0028
#define ICACHE_WCAP_ADDR_OFFSET 0
#define ICACHE_WCAP_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DCACHE_MADDR_ADDR 0x002c
#define DCACHE_WCAP_ADDR_OFFSET 0
#define DCACHE_WCAP_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_AHB_LP_CTRL_ADDR 0x0030
#define CHIP_DEEP_SLEEP_ENA_OFFSET 10
#define CHIP_DEEP_SLEEP_ENA_MASK 0x00000400
#define AHB_SYS_SLEEP_ENA_OFFSET 9
#define AHB_SYS_SLEEP_ENA_MASK 0x00000200
#define RV_CORE0_SLEEP_ENA_OFFSET 8
#define RV_CORE0_SLEEP_ENA_MASK 0x00000100
#define CHIP_DEEP_STOP_OFFSET 2
#define CHIP_DEEP_STOP_MASK 0x00000004
#define AHB_SYS_STOP_OFFSET 1
#define AHB_SYS_STOP_MASK 0x00000002
#define RV_CORE0_STOP_OFFSET 0
#define RV_CORE0_STOP_MASK 0x00000001

//-----------------------------------
#define CFG_AHB_MEM_CTRL_ADDR 0x0034
#define IIS_RAM_FORCE_ON_OFFSET 24
#define IIS_RAM_FORCE_ON_MASK 0x01000000
#define HRAM3_ADC_MODE_OFFSET 23
#define HRAM3_ADC_MODE_MASK 0x00800000
#define HRAM2_ADC_MODE_OFFSET 22
#define HRAM2_ADC_MODE_MASK 0x00400000
#define HRAM1_ADC_MODE_OFFSET 21
#define HRAM1_ADC_MODE_MASK 0x00200000
#define HRAM0_ADC_MODE_OFFSET 20
#define HRAM0_ADC_MODE_MASK 0x00100000
#define UART_RAM_FORCE_ON_OFFSET 19
#define UART_RAM_FORCE_ON_MASK 0x00080000
#define GMAC_RX_BUF_FORCE_ON_OFFSET 18
#define GMAC_RX_BUF_FORCE_ON_MASK 0x00040000
#define GMAC_TX_BUF_FORCE_ON_OFFSET 17
#define GMAC_TX_BUF_FORCE_ON_MASK 0x00020000
#define EMC_BUF_FORCE_ON_OFFSET 16
#define EMC_BUF_FORCE_ON_MASK 0x00010000
#define DCACHE_DMEM3_FORCE_ON_OFFSET 15
#define DCACHE_DMEM3_FORCE_ON_MASK 0x00008000
#define DCACHE_DMEM2_FORCE_ON_OFFSET 14
#define DCACHE_DMEM2_FORCE_ON_MASK 0x00004000
#define DCACHE_DMEM1_FORCE_ON_OFFSET 13
#define DCACHE_DMEM1_FORCE_ON_MASK 0x00002000
#define DCACHE_DMEM0_FORCE_ON_OFFSET 12
#define DCACHE_DMEM0_FORCE_ON_MASK 0x00001000
#define DCACHE_TMEM1_FORCE_ON_OFFSET 11
#define DCACHE_TMEM1_FORCE_ON_MASK 0x00000800
#define DCACHE_TMEM0_FORCE_ON_OFFSET 10
#define DCACHE_TMEM0_FORCE_ON_MASK 0x00000400
#define ICACHE_DMEM1_FORCE_ON_OFFSET 9
#define ICACHE_DMEM1_FORCE_ON_MASK 0x00000200
#define ICACHE_DMEM0_FORCE_ON_OFFSET 8
#define ICACHE_DMEM0_FORCE_ON_MASK 0x00000100
#define ICACHE_TMEM_FORCE_ON_OFFSET 7
#define ICACHE_TMEM_FORCE_ON_MASK 0x00000080
#define HROM1_FORCE_ON_OFFSET 6
#define HROM1_FORCE_ON_MASK 0x00000040
#define HROM0_FORCE_ON_OFFSET 5
#define HROM0_FORCE_ON_MASK 0x00000020
#define SEC_RAM_FORCE_ON_OFFSET 4
#define SEC_RAM_FORCE_ON_MASK 0x00000010
#define HRAM3_FORCE_ON_OFFSET 3
#define HRAM3_FORCE_ON_MASK 0x00000008
#define HRAM2_FORCE_ON_OFFSET 2
#define HRAM2_FORCE_ON_MASK 0x00000004
#define HRAM1_FORCE_ON_OFFSET 1
#define HRAM1_FORCE_ON_MASK 0x00000002
#define HRAM0_FORCE_ON_OFFSET 0
#define HRAM0_FORCE_ON_MASK 0x00000001

//-----------------------------------
#define CFG_IC_MON_SADDR_ADDR 0x0038
#define ICACHE_MON_SADDR_OFFSET 0
#define ICACHE_MON_SADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_IC_MON_EADDR_ADDR 0x003c
#define ICACHE_MON_EADDR_OFFSET 0
#define ICACHE_MON_EADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DC_MON_SADDR_ADDR 0x0040
#define DCACHE_MON_SADDR_OFFSET 0
#define DCACHE_MON_SADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DC_MON_EADDR_ADDR 0x0044
#define DCACHE_MON_EADDR_OFFSET 0
#define DCACHE_MON_EADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DBG_CTR1_ADDR 0x0048
#define CHIP_DBG_SIG_SEL_OFFSET 16
#define CHIP_DBG_SIG_SEL_MASK 0x00FF0000
#define CHIP_DBG_BUS_SEL_OFFSET 8
#define CHIP_DBG_BUS_SEL_MASK 0x0000FF00
#define DBG_BUS_TEST_OFFSET 0
#define DBG_BUS_TEST_MASK 0x00000001

//-----------------------------------
#define CFG_CPU1_START_PC_ADDR 0x004c
#define CORE1_START_PC_OFFSET 0
#define CORE1_START_PC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RST_FLAG_ADDR 0x0050
#define CORE1_SOFT_RST_FLAG_CLR_OFFSET 26
#define CORE1_SOFT_RST_FLAG_CLR_MASK 0x04000000
#define CORE0_SOFT_RST_FLAG_CLR_OFFSET 25
#define CORE0_SOFT_RST_FLAG_CLR_MASK 0x02000000
#define DEBUG1_IO_FULLRESET_FLAG_CLR_OFFSET 24
#define DEBUG1_IO_FULLRESET_FLAG_CLR_MASK 0x01000000
#define DEBUG0_IO_FULLRESET_FLAG_CLR_OFFSET 23
#define DEBUG0_IO_FULLRESET_FLAG_CLR_MASK 0x00800000
#define DEBUG1_IO_NDRESET_FLAG_CLR_OFFSET 22
#define DEBUG1_IO_NDRESET_FLAG_CLR_MASK 0x00400000
#define DEBUG0_IO_NDRESET_FLAG_CLR_OFFSET 21
#define DEBUG0_IO_NDRESET_FLAG_CLR_MASK 0x00200000
#define WDG1_FULLRST_FLAG_CLR_OFFSET 20
#define WDG1_FULLRST_FLAG_CLR_MASK 0x00100000
#define WDG0_FULLRST_FLAG_CLR_OFFSET 19
#define WDG0_FULLRST_FLAG_CLR_MASK 0x00080000
#define WDG1_CPURST_FLAG_CLR_OFFSET 18
#define WDG1_CPURST_FLAG_CLR_MASK 0x00040000
#define WDG0_CPURST_FLAG_CLR_OFFSET 17
#define WDG0_CPURST_FLAG_CLR_MASK 0x00020000
#define POR_RST_FLAG_CLR_OFFSET 16
#define POR_RST_FLAG_CLR_MASK 0x00010000
#define CORE1_SOFT_RST_FLAG_OFFSET 10
#define CORE1_SOFT_RST_FLAG_MASK 0x00000400
#define CORE0_SOFT_RST_FLAG_OFFSET 9
#define CORE0_SOFT_RST_FLAG_MASK 0x00000200
#define DEBUG1_IO_FULLRESET_FLAG_OFFSET 8
#define DEBUG1_IO_FULLRESET_FLAG_MASK 0x00000100
#define DEBUG0_IO_FULLRESET_FLAG_OFFSET 7
#define DEBUG0_IO_FULLRESET_FLAG_MASK 0x00000080
#define DEBUG1_IO_NDRESET_FLAG_OFFSET 6
#define DEBUG1_IO_NDRESET_FLAG_MASK 0x00000040
#define DEBUG0_IO_NDRESET_FLAG_OFFSET 5
#define DEBUG0_IO_NDRESET_FLAG_MASK 0x00000020
#define WDG1_FULLRST_FLAG_OFFSET 4
#define WDG1_FULLRST_FLAG_MASK 0x00000010
#define WDG0_FULLRST_FLAG_OFFSET 3
#define WDG0_FULLRST_FLAG_MASK 0x00000008
#define WDG1_CPURST_FLAG_OFFSET 2
#define WDG1_CPURST_FLAG_MASK 0x00000004
#define WDG0_CPURST_FLAG_OFFSET 1
#define WDG0_CPURST_FLAG_MASK 0x00000002
#define POR_RST_FLAG_OFFSET 0
#define POR_RST_FLAG_MASK 0x00000001

//-----------------------------------
#define CFG_AHB_MTX_PRI_CFG_ADDR 0x0054
#define MTX_M11_PRI_SEL_OFFSET 14
#define MTX_M11_PRI_SEL_MASK 0x0000C000
#define MTX_M11_PRI_RND_EN_OFFSET 13
#define MTX_M11_PRI_RND_EN_MASK 0x00002000
#define MTX_M11_PRI_ADJ_EN_OFFSET 12
#define MTX_M11_PRI_ADJ_EN_MASK 0x00001000
#define MTX_M11_PRI_RND_TH_OFFSET 8
#define MTX_M11_PRI_RND_TH_MASK 0x00000F00
#define MTX_M10_PRI_SEL_OFFSET 6
#define MTX_M10_PRI_SEL_MASK 0x000000C0
#define MTX_M10_PRI_RND_EN_OFFSET 5
#define MTX_M10_PRI_RND_EN_MASK 0x00000020
#define MTX_M10_PRI_ADJ_EN_OFFSET 4
#define MTX_M10_PRI_ADJ_EN_MASK 0x00000010
#define MTX_M10_PRI_RND_TH_OFFSET 0
#define MTX_M10_PRI_RND_TH_MASK 0x0000000F

//HW module read/write macro
#define AHB_RF_READ_REG(addr) SOC_READ_REG(AHB_RF_BASEADDR + addr)
#define AHB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_RF_BASEADDR + addr,value)