kunlun/inc/hw/reg/riscv/13/gpio_mtx_reg.h

//-----------------------------------
#define CFG_SIG0_IN_CFG_ADDR 0x0
#define SIG0_IN_CORE_SEL_OFFSET 12
#define SIG0_IN_CORE_SEL_MASK 0x00001000
#define SIG0_IN_DEF_SEL_OFFSET 8
#define SIG0_IN_DEF_SEL_MASK 0x00000300
#define SIG0_IN_GPIO_SEL_OFFSET 0
#define SIG0_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG1_IN_CFG_ADDR 0x4
#define SIG1_IN_CORE_SEL_OFFSET 12
#define SIG1_IN_CORE_SEL_MASK 0x00001000
#define SIG1_IN_DEF_SEL_OFFSET 8
#define SIG1_IN_DEF_SEL_MASK 0x00000300
#define SIG1_IN_GPIO_SEL_OFFSET 0
#define SIG1_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG2_IN_CFG_ADDR 0x8
#define SIG2_IN_CORE_SEL_OFFSET 12
#define SIG2_IN_CORE_SEL_MASK 0x00001000
#define SIG2_IN_DEF_SEL_OFFSET 8
#define SIG2_IN_DEF_SEL_MASK 0x00000300
#define SIG2_IN_GPIO_SEL_OFFSET 0
#define SIG2_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG3_IN_CFG_ADDR 0xc
#define SIG3_IN_CORE_SEL_OFFSET 12
#define SIG3_IN_CORE_SEL_MASK 0x00001000
#define SIG3_IN_DEF_SEL_OFFSET 8
#define SIG3_IN_DEF_SEL_MASK 0x00000300
#define SIG3_IN_GPIO_SEL_OFFSET 0
#define SIG3_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG4_IN_CFG_ADDR 0x10
#define SIG4_IN_CORE_SEL_OFFSET 12
#define SIG4_IN_CORE_SEL_MASK 0x00001000
#define SIG4_IN_DEF_SEL_OFFSET 8
#define SIG4_IN_DEF_SEL_MASK 0x00000300
#define SIG4_IN_GPIO_SEL_OFFSET 0
#define SIG4_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG5_IN_CFG_ADDR 0x14
#define SIG5_IN_CORE_SEL_OFFSET 12
#define SIG5_IN_CORE_SEL_MASK 0x00001000
#define SIG5_IN_DEF_SEL_OFFSET 8
#define SIG5_IN_DEF_SEL_MASK 0x00000300
#define SIG5_IN_GPIO_SEL_OFFSET 0
#define SIG5_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG6_IN_CFG_ADDR 0x18
#define SIG6_IN_CORE_SEL_OFFSET 12
#define SIG6_IN_CORE_SEL_MASK 0x00001000
#define SIG6_IN_DEF_SEL_OFFSET 8
#define SIG6_IN_DEF_SEL_MASK 0x00000300
#define SIG6_IN_GPIO_SEL_OFFSET 0
#define SIG6_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG7_IN_CFG_ADDR 0x1c
#define SIG7_IN_CORE_SEL_OFFSET 12
#define SIG7_IN_CORE_SEL_MASK 0x00001000
#define SIG7_IN_DEF_SEL_OFFSET 8
#define SIG7_IN_DEF_SEL_MASK 0x00000300
#define SIG7_IN_GPIO_SEL_OFFSET 0
#define SIG7_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG8_IN_CFG_ADDR 0x20
#define SIG8_IN_CORE_SEL_OFFSET 12
#define SIG8_IN_CORE_SEL_MASK 0x00001000
#define SIG8_IN_DEF_SEL_OFFSET 8
#define SIG8_IN_DEF_SEL_MASK 0x00000300
#define SIG8_IN_GPIO_SEL_OFFSET 0
#define SIG8_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG9_IN_CFG_ADDR 0x24
#define SIG9_IN_CORE_SEL_OFFSET 12
#define SIG9_IN_CORE_SEL_MASK 0x00001000
#define SIG9_IN_DEF_SEL_OFFSET 8
#define SIG9_IN_DEF_SEL_MASK 0x00000300
#define SIG9_IN_GPIO_SEL_OFFSET 0
#define SIG9_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG10_IN_CFG_ADDR 0x28
#define SIG10_IN_DEF_SEL_OFFSET 8
#define SIG10_IN_DEF_SEL_MASK 0x00000300
#define SIG10_IN_GPIO_SEL_OFFSET 0
#define SIG10_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG11_IN_CFG_ADDR 0x2c
#define SIG11_IN_DEF_SEL_OFFSET 8
#define SIG11_IN_DEF_SEL_MASK 0x00000300
#define SIG11_IN_GPIO_SEL_OFFSET 0
#define SIG11_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG12_IN_CFG_ADDR 0x30
#define SIG12_IN_DEF_SEL_OFFSET 8
#define SIG12_IN_DEF_SEL_MASK 0x00000300
#define SIG12_IN_GPIO_SEL_OFFSET 0
#define SIG12_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG13_IN_CFG_ADDR 0x34
#define SIG13_IN_DEF_SEL_OFFSET 8
#define SIG13_IN_DEF_SEL_MASK 0x00000300
#define SIG13_IN_GPIO_SEL_OFFSET 0
#define SIG13_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG14_IN_CFG_ADDR 0x38
#define SIG14_IN_DEF_SEL_OFFSET 8
#define SIG14_IN_DEF_SEL_MASK 0x00000300
#define SIG14_IN_GPIO_SEL_OFFSET 0
#define SIG14_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG15_IN_CFG_ADDR 0x3c
#define SIG15_IN_DEF_SEL_OFFSET 8
#define SIG15_IN_DEF_SEL_MASK 0x00000300
#define SIG15_IN_GPIO_SEL_OFFSET 0
#define SIG15_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG16_IN_CFG_ADDR 0x40
#define SIG16_IN_DEF_SEL_OFFSET 8
#define SIG16_IN_DEF_SEL_MASK 0x00000300
#define SIG16_IN_GPIO_SEL_OFFSET 0
#define SIG16_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG17_IN_CFG_ADDR 0x44
#define SIG17_IN_DEF_SEL_OFFSET 8
#define SIG17_IN_DEF_SEL_MASK 0x00000300
#define SIG17_IN_GPIO_SEL_OFFSET 0
#define SIG17_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG18_IN_CFG_ADDR 0x48
#define SIG18_IN_DEF_SEL_OFFSET 8
#define SIG18_IN_DEF_SEL_MASK 0x00000300
#define SIG18_IN_GPIO_SEL_OFFSET 0
#define SIG18_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG19_IN_CFG_ADDR 0x4c
#define SIG19_IN_DEF_SEL_OFFSET 8
#define SIG19_IN_DEF_SEL_MASK 0x00000300
#define SIG19_IN_GPIO_SEL_OFFSET 0
#define SIG19_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG20_IN_CFG_ADDR 0x50
#define SIG20_IN_DEF_SEL_OFFSET 8
#define SIG20_IN_DEF_SEL_MASK 0x00000300
#define SIG20_IN_GPIO_SEL_OFFSET 0
#define SIG20_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG21_IN_CFG_ADDR 0x54
#define SIG21_IN_DEF_SEL_OFFSET 8
#define SIG21_IN_DEF_SEL_MASK 0x00000300
#define SIG21_IN_GPIO_SEL_OFFSET 0
#define SIG21_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG22_IN_CFG_ADDR 0x58
#define SIG22_IN_DEF_SEL_OFFSET 8
#define SIG22_IN_DEF_SEL_MASK 0x00000300
#define SIG22_IN_GPIO_SEL_OFFSET 0
#define SIG22_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG23_IN_CFG_ADDR 0x5c
#define SIG23_IN_DEF_SEL_OFFSET 8
#define SIG23_IN_DEF_SEL_MASK 0x00000300
#define SIG23_IN_GPIO_SEL_OFFSET 0
#define SIG23_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG24_IN_CFG_ADDR 0x60
#define SIG24_IN_DEF_SEL_OFFSET 8
#define SIG24_IN_DEF_SEL_MASK 0x00000300
#define SIG24_IN_GPIO_SEL_OFFSET 0
#define SIG24_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG25_IN_CFG_ADDR 0x64
#define SIG25_IN_DEF_SEL_OFFSET 8
#define SIG25_IN_DEF_SEL_MASK 0x00000300
#define SIG25_IN_GPIO_SEL_OFFSET 0
#define SIG25_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG26_IN_CFG_ADDR 0x68
#define SIG26_IN_DEF_SEL_OFFSET 8
#define SIG26_IN_DEF_SEL_MASK 0x00000300
#define SIG26_IN_GPIO_SEL_OFFSET 0
#define SIG26_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG27_IN_CFG_ADDR 0x6c
#define SIG27_IN_DEF_SEL_OFFSET 8
#define SIG27_IN_DEF_SEL_MASK 0x00000300
#define SIG27_IN_GPIO_SEL_OFFSET 0
#define SIG27_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG28_IN_CFG_ADDR 0x70
#define SIG28_IN_DEF_SEL_OFFSET 8
#define SIG28_IN_DEF_SEL_MASK 0x00000300
#define SIG28_IN_GPIO_SEL_OFFSET 0
#define SIG28_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG29_IN_CFG_ADDR 0x74
#define SIG29_IN_DEF_SEL_OFFSET 8
#define SIG29_IN_DEF_SEL_MASK 0x00000300
#define SIG29_IN_GPIO_SEL_OFFSET 0
#define SIG29_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG30_IN_CFG_ADDR 0x78
#define SIG30_IN_DEF_SEL_OFFSET 8
#define SIG30_IN_DEF_SEL_MASK 0x00000300
#define SIG30_IN_GPIO_SEL_OFFSET 0
#define SIG30_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG31_IN_CFG_ADDR 0x7c
#define SIG31_IN_DEF_SEL_OFFSET 8
#define SIG31_IN_DEF_SEL_MASK 0x00000300
#define SIG31_IN_GPIO_SEL_OFFSET 0
#define SIG31_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG32_IN_CFG_ADDR 0x80
#define SIG32_IN_DEF_SEL_OFFSET 8
#define SIG32_IN_DEF_SEL_MASK 0x00000300
#define SIG32_IN_GPIO_SEL_OFFSET 0
#define SIG32_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG33_IN_CFG_ADDR 0x84
#define SIG33_IN_DEF_SEL_OFFSET 8
#define SIG33_IN_DEF_SEL_MASK 0x00000300
#define SIG33_IN_GPIO_SEL_OFFSET 0
#define SIG33_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG34_IN_CFG_ADDR 0x88
#define SIG34_IN_DEF_SEL_OFFSET 8
#define SIG34_IN_DEF_SEL_MASK 0x00000300
#define SIG34_IN_GPIO_SEL_OFFSET 0
#define SIG34_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG35_IN_CFG_ADDR 0x8c
#define SIG35_IN_DEF_SEL_OFFSET 8
#define SIG35_IN_DEF_SEL_MASK 0x00000300
#define SIG35_IN_GPIO_SEL_OFFSET 0
#define SIG35_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG36_IN_CFG_ADDR 0x90
#define SIG36_IN_DEF_SEL_OFFSET 8
#define SIG36_IN_DEF_SEL_MASK 0x00000300
#define SIG36_IN_GPIO_SEL_OFFSET 0
#define SIG36_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG37_IN_CFG_ADDR 0x94
#define SIG37_IN_DEF_SEL_OFFSET 8
#define SIG37_IN_DEF_SEL_MASK 0x00000300
#define SIG37_IN_GPIO_SEL_OFFSET 0
#define SIG37_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG38_IN_CFG_ADDR 0x98
#define SIG38_IN_DEF_SEL_OFFSET 8
#define SIG38_IN_DEF_SEL_MASK 0x00000300
#define SIG38_IN_GPIO_SEL_OFFSET 0
#define SIG38_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG39_IN_CFG_ADDR 0x9c
#define SIG39_IN_DEF_SEL_OFFSET 8
#define SIG39_IN_DEF_SEL_MASK 0x00000300
#define SIG39_IN_GPIO_SEL_OFFSET 0
#define SIG39_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG40_IN_CFG_ADDR 0xa0
#define SIG40_IN_DEF_SEL_OFFSET 8
#define SIG40_IN_DEF_SEL_MASK 0x00000300
#define SIG40_IN_GPIO_SEL_OFFSET 0
#define SIG40_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG41_IN_CFG_ADDR 0xa4
#define SIG41_IN_DEF_SEL_OFFSET 8
#define SIG41_IN_DEF_SEL_MASK 0x00000300
#define SIG41_IN_GPIO_SEL_OFFSET 0
#define SIG41_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG42_IN_CFG_ADDR 0xa8
#define SIG42_IN_DEF_SEL_OFFSET 8
#define SIG42_IN_DEF_SEL_MASK 0x00000300
#define SIG42_IN_GPIO_SEL_OFFSET 0
#define SIG42_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG43_IN_CFG_ADDR 0xac
#define SIG43_IN_DEF_SEL_OFFSET 8
#define SIG43_IN_DEF_SEL_MASK 0x00000300
#define SIG43_IN_GPIO_SEL_OFFSET 0
#define SIG43_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG44_IN_CFG_ADDR 0xb0
#define SIG44_IN_DEF_SEL_OFFSET 8
#define SIG44_IN_DEF_SEL_MASK 0x00000300
#define SIG44_IN_GPIO_SEL_OFFSET 0
#define SIG44_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG45_IN_CFG_ADDR 0xb4
#define SIG45_IN_DEF_SEL_OFFSET 8
#define SIG45_IN_DEF_SEL_MASK 0x00000300
#define SIG45_IN_GPIO_SEL_OFFSET 0
#define SIG45_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG46_IN_CFG_ADDR 0xb8
#define SIG46_IN_DEF_SEL_OFFSET 8
#define SIG46_IN_DEF_SEL_MASK 0x00000300
#define SIG46_IN_GPIO_SEL_OFFSET 0
#define SIG46_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG47_IN_CFG_ADDR 0xbc
#define SIG47_IN_DEF_SEL_OFFSET 8
#define SIG47_IN_DEF_SEL_MASK 0x00000300
#define SIG47_IN_GPIO_SEL_OFFSET 0
#define SIG47_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG48_IN_CFG_ADDR 0xc0
#define SIG48_IN_CORE_SEL_OFFSET 12
#define SIG48_IN_CORE_SEL_MASK 0x00001000
#define SIG48_IN_DEF_SEL_OFFSET 8
#define SIG48_IN_DEF_SEL_MASK 0x00000300
#define SIG48_IN_GPIO_SEL_OFFSET 0
#define SIG48_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG49_IN_CFG_ADDR 0xc4
#define SIG49_IN_CORE_SEL_OFFSET 12
#define SIG49_IN_CORE_SEL_MASK 0x00001000
#define SIG49_IN_DEF_SEL_OFFSET 8
#define SIG49_IN_DEF_SEL_MASK 0x00000300
#define SIG49_IN_GPIO_SEL_OFFSET 0
#define SIG49_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG50_IN_CFG_ADDR 0xc8
#define SIG50_IN_CORE_SEL_OFFSET 12
#define SIG50_IN_CORE_SEL_MASK 0x00001000
#define SIG50_IN_DEF_SEL_OFFSET 8
#define SIG50_IN_DEF_SEL_MASK 0x00000300
#define SIG50_IN_GPIO_SEL_OFFSET 0
#define SIG50_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG51_IN_CFG_ADDR 0xcc
#define SIG51_IN_CORE_SEL_OFFSET 12
#define SIG51_IN_CORE_SEL_MASK 0x00001000
#define SIG51_IN_DEF_SEL_OFFSET 8
#define SIG51_IN_DEF_SEL_MASK 0x00000300
#define SIG51_IN_GPIO_SEL_OFFSET 0
#define SIG51_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG52_IN_CFG_ADDR 0xd0
#define SIG52_IN_DEF_SEL_OFFSET 8
#define SIG52_IN_DEF_SEL_MASK 0x00000300
#define SIG52_IN_GPIO_SEL_OFFSET 0
#define SIG52_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG53_IN_CFG_ADDR 0xd4
#define SIG53_IN_DEF_SEL_OFFSET 8
#define SIG53_IN_DEF_SEL_MASK 0x00000300
#define SIG53_IN_GPIO_SEL_OFFSET 0
#define SIG53_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_SIG54_IN_CFG_ADDR 0xd8
#define SIG54_IN_DEF_SEL_OFFSET 8
#define SIG54_IN_DEF_SEL_MASK 0x00000300
#define SIG54_IN_GPIO_SEL_OFFSET 0
#define SIG54_IN_GPIO_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO0_OUT_CFG_ADDR 0xdc
#define GPIO0_OUT_SEL_OFFSET 0
#define GPIO0_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO1_OUT_CFG_ADDR 0xe0
#define GPIO1_OUT_SEL_OFFSET 0
#define GPIO1_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO2_OUT_CFG_ADDR 0xe4
#define GPIO2_OUT_SEL_OFFSET 0
#define GPIO2_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO3_OUT_CFG_ADDR 0xe8
#define GPIO3_OUT_SEL_OFFSET 0
#define GPIO3_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO4_OUT_CFG_ADDR 0xec
#define GPIO4_OUT_SEL_OFFSET 0
#define GPIO4_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO5_OUT_CFG_ADDR 0xf0
#define GPIO5_OUT_SEL_OFFSET 0
#define GPIO5_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO6_OUT_CFG_ADDR 0xf4
#define GPIO6_OUT_SEL_OFFSET 0
#define GPIO6_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO7_OUT_CFG_ADDR 0xf8
#define GPIO7_OUT_SEL_OFFSET 0
#define GPIO7_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO8_OUT_CFG_ADDR 0xfc
#define GPIO8_OUT_SEL_OFFSET 0
#define GPIO8_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO9_OUT_CFG_ADDR 0x100
#define GPIO9_OUT_SEL_OFFSET 0
#define GPIO9_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO10_OUT_CFG_ADDR 0x104
#define GPIO10_OUT_SEL_OFFSET 0
#define GPIO10_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO11_OUT_CFG_ADDR 0x108
#define GPIO11_OUT_SEL_OFFSET 0
#define GPIO11_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO12_OUT_CFG_ADDR 0x10c
#define GPIO12_OUT_SEL_OFFSET 0
#define GPIO12_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO13_OUT_CFG_ADDR 0x110
#define GPIO13_OUT_SEL_OFFSET 0
#define GPIO13_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO14_OUT_CFG_ADDR 0x114
#define GPIO14_OUT_SEL_OFFSET 0
#define GPIO14_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO15_OUT_CFG_ADDR 0x118
#define GPIO15_OUT_SEL_OFFSET 0
#define GPIO15_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO16_OUT_CFG_ADDR 0x11c
#define GPIO16_OUT_SEL_OFFSET 0
#define GPIO16_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO17_OUT_CFG_ADDR 0x120
#define GPIO17_OUT_SEL_OFFSET 0
#define GPIO17_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO18_OUT_CFG_ADDR 0x124
#define GPIO18_OUT_SEL_OFFSET 0
#define GPIO18_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO19_OUT_CFG_ADDR 0x128
#define GPIO19_OUT_SEL_OFFSET 0
#define GPIO19_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO20_OUT_CFG_ADDR 0x12c
#define GPIO20_OUT_SEL_OFFSET 0
#define GPIO20_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO21_OUT_CFG_ADDR 0x130
#define GPIO21_OUT_SEL_OFFSET 0
#define GPIO21_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO22_OUT_CFG_ADDR 0x134
#define GPIO22_OUT_SEL_OFFSET 0
#define GPIO22_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO23_OUT_CFG_ADDR 0x138
#define GPIO23_OUT_SEL_OFFSET 0
#define GPIO23_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO24_OUT_CFG_ADDR 0x13c
#define GPIO24_OUT_SEL_OFFSET 0
#define GPIO24_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO25_OUT_CFG_ADDR 0x140
#define GPIO25_OUT_SEL_OFFSET 0
#define GPIO25_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO26_OUT_CFG_ADDR 0x144
#define GPIO26_OUT_SEL_OFFSET 0
#define GPIO26_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO27_OUT_CFG_ADDR 0x148
#define GPIO27_OUT_SEL_OFFSET 0
#define GPIO27_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO28_OUT_CFG_ADDR 0x14c
#define GPIO28_OUT_SEL_OFFSET 0
#define GPIO28_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO29_OUT_CFG_ADDR 0x150
#define GPIO29_OUT_SEL_OFFSET 0
#define GPIO29_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO30_OUT_CFG_ADDR 0x154
#define GPIO30_OUT_SEL_OFFSET 0
#define GPIO30_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO31_OUT_CFG_ADDR 0x158
#define GPIO31_OUT_SEL_OFFSET 0
#define GPIO31_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO32_OUT_CFG_ADDR 0x15c
#define GPIO32_OUT_SEL_OFFSET 0
#define GPIO32_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO33_OUT_CFG_ADDR 0x160
#define GPIO33_OUT_SEL_OFFSET 0
#define GPIO33_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO34_OUT_CFG_ADDR 0x164
#define GPIO34_OUT_SEL_OFFSET 0
#define GPIO34_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO35_OUT_CFG_ADDR 0x168
#define GPIO35_OUT_SEL_OFFSET 0
#define GPIO35_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO36_OUT_CFG_ADDR 0x16c
#define GPIO36_OUT_SEL_OFFSET 0
#define GPIO36_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO37_OUT_CFG_ADDR 0x170
#define GPIO37_OUT_SEL_OFFSET 0
#define GPIO37_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO38_OUT_CFG_ADDR 0x174
#define GPIO38_OUT_SEL_OFFSET 0
#define GPIO38_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO39_OUT_CFG_ADDR 0x178
#define GPIO39_OUT_SEL_OFFSET 0
#define GPIO39_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO40_OUT_CFG_ADDR 0x17c
#define GPIO40_OUT_SEL_OFFSET 0
#define GPIO40_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO41_OUT_CFG_ADDR 0x180
#define GPIO41_OUT_SEL_OFFSET 0
#define GPIO41_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO42_OUT_CFG_ADDR 0x184
#define GPIO42_OUT_SEL_OFFSET 0
#define GPIO42_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO43_OUT_CFG_ADDR 0x188
#define GPIO43_OUT_SEL_OFFSET 0
#define GPIO43_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO44_OUT_CFG_ADDR 0x18c
#define GPIO44_OUT_SEL_OFFSET 0
#define GPIO44_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO45_OUT_CFG_ADDR 0x190
#define GPIO45_OUT_SEL_OFFSET 0
#define GPIO45_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO46_OUT_CFG_ADDR 0x194
#define GPIO46_OUT_SEL_OFFSET 0
#define GPIO46_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO47_OUT_CFG_ADDR 0x198
#define GPIO47_OUT_SEL_OFFSET 0
#define GPIO47_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO48_OUT_CFG_ADDR 0x19c
#define GPIO48_OUT_SEL_OFFSET 0
#define GPIO48_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO49_OUT_CFG_ADDR 0x1a0
#define GPIO49_OUT_SEL_OFFSET 0
#define GPIO49_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO50_OUT_CFG_ADDR 0x1a4
#define GPIO50_OUT_SEL_OFFSET 0
#define GPIO50_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO51_OUT_CFG_ADDR 0x1a8
#define GPIO51_OUT_SEL_OFFSET 0
#define GPIO51_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO52_OUT_CFG_ADDR 0x1ac
#define GPIO52_OUT_SEL_OFFSET 0
#define GPIO52_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO53_OUT_CFG_ADDR 0x1b0
#define GPIO53_OUT_SEL_OFFSET 0
#define GPIO53_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO54_OUT_CFG_ADDR 0x1b4
#define GPIO54_OUT_SEL_OFFSET 0
#define GPIO54_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO55_OUT_CFG_ADDR 0x1b8
#define GPIO55_OUT_SEL_OFFSET 0
#define GPIO55_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO56_OUT_CFG_ADDR 0x1bc
#define GPIO56_OUT_SEL_OFFSET 0
#define GPIO56_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO57_OUT_CFG_ADDR 0x1c0
#define GPIO57_OUT_SEL_OFFSET 0
#define GPIO57_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO58_OUT_CFG_ADDR 0x1c4
#define GPIO58_OUT_SEL_OFFSET 0
#define GPIO58_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO59_OUT_CFG_ADDR 0x1c8
#define GPIO59_OUT_SEL_OFFSET 0
#define GPIO59_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO60_OUT_CFG_ADDR 0x1cc
#define GPIO60_OUT_SEL_OFFSET 0
#define GPIO60_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO61_OUT_CFG_ADDR 0x1d0
#define GPIO61_OUT_SEL_OFFSET 0
#define GPIO61_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO62_OUT_CFG_ADDR 0x1d4
#define GPIO62_OUT_SEL_OFFSET 0
#define GPIO62_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO63_OUT_CFG_ADDR 0x1d8
#define GPIO63_OUT_SEL_OFFSET 0
#define GPIO63_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO64_OUT_CFG_ADDR 0x1dc
#define GPIO64_OUT_SEL_OFFSET 0
#define GPIO64_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO65_OUT_CFG_ADDR 0x1e0
#define GPIO65_OUT_SEL_OFFSET 0
#define GPIO65_OUT_SEL_MASK 0x000000FF

//-----------------------------------
#define CFG_GPIO66_OUT_CFG_ADDR 0x1e4
#define GPIO66_OUT_SEL_OFFSET 0
#define GPIO66_OUT_SEL_MASK 0x000000FF

//HW module read/write macro
#define GPIO_MTX_READ_REG(addr) SOC_READ_REG(GPIO_MTX_BASEADDR + addr)
#define GPIO_MTX_WRITE_REG(addr,value) SOC_WRITE_REG(GPIO_MTX_BASEADDR + addr,value)