kunlun/inc/hw/reg/riscv/14/rgf_mac_tx_desc.h

//-----------------------------------
#define CFG_START_WORD0_ADDR 0x0000
#define PPDU_MODE_OFFSET 29
#define PPDU_MODE_MASK 0xE0000000
#define PB_NUM_OFFSET 26
#define PB_NUM_MASK 0x1C000000
#define NEED_ACK_OFFSET 25
#define NEED_ACK_MASK 0x02000000
#define SG_BANDSEL_OFFSET 23
#define SG_BANDSEL_MASK 0x01800000
#define TX_RATE_MODE_OFFSET 21
#define TX_RATE_MODE_MASK 0x00600000
#define TX_PB_MODULATION_OFFSET 18
#define TX_PB_MODULATION_MASK 0x001C0000
#define NEED_ENCRY_OFFSET 17
#define NEED_ENCRY_MASK 0x00020000
#define TX_PHASE_OFFSET 15
#define TX_PHASE_MASK 0x00018000
#define TX_POWER_OFFSET 7
#define TX_POWER_MASK 0x00007F80
#define TX_PORT_OFFSET 5
#define TX_PORT_MASK 0x00000060
#define PROTO_TYPE_OFFSET 2
#define PROTO_TYPE_MASK 0x0000001C
#define DESC_TYPE_OFFSET 0
#define DESC_TYPE_MASK 0x00000003

//-----------------------------------
#define CFG_START_WORD1_ADDR 0x0004
#define PB_HDR_CRC_LEN_OFFSET 28
#define PB_HDR_CRC_LEN_MASK 0xF0000000
#define SW_TX_FL_PPB_OFFSET 14
#define SW_TX_FL_PPB_MASK 0x0FFFC000
#define TX_SYMBNUM_PPB_OFFSET 5
#define TX_SYMBNUM_PPB_MASK 0x00003FE0
#define TX_TONE_AMP_OFFSET 0
#define TX_TONE_AMP_MASK 0x0000001F

//-----------------------------------
#define CFG_START_WORD2_ADDR 0x0008
#define NEXT_OFFSET 0
#define NEXT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD3_ADDR 0x000C
#define TX_STATUS_OFFSET 0
#define TX_STATUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD4_ADDR 0x0010
#define PB_LIST_OFFSET 0
#define PB_LIST_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD5_ADDR 0x0014
#define FC0_OFFSET 0
#define FC0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD6_ADDR 0x0018
#define FC1_OFFSET 0
#define FC1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD7_ADDR 0x001C
#define FC2_OFFSET 0
#define FC2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD8_ADDR 0x0020
#define FC3_OFFSET 0
#define FC3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD9_ADDR 0x0024
#define OFFSET_OFFSET 16
#define OFFSET_MASK 0xFFFF0000
#define TOTAL_BYTES_OFFSET 3
#define TOTAL_BYTES_MASK 0x0000FFF8
#define SW_PB_CRC_OFFSET 2
#define SW_PB_CRC_MASK 0x00000004
#define SW_FC_CRC_OFFSET 1
#define SW_FC_CRC_MASK 0x00000002
#define RESV0_OFFSET 0
#define RESV0_MASK 0x00000001

//-----------------------------------
#define CFG_START_WORD10_ADDR 0x0028
#define START_TIME_OFFSET 0
#define START_TIME_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_START_WORD11_ADDR 0x002C
#define RESV11_OFFSET 5
#define RESV11_MASK 0xFFFFFFE0
#define SWQ_ID_OFFSET 0
#define SWQ_ID_MASK 0x0000001F

//-----------------------------------
#define CFG_START_WORD12_ADDR 0x0030
#define SW_BUF_OFFSET_OFFSET 20
#define SW_BUF_OFFSET_MASK 0xFFF00000
#define PAUSE_ON_XTRETRY_OFFSET 19
#define PAUSE_ON_XTRETRY_MASK 0x00080000
#define TX_DESC_REUSE_OFFSET 18
#define TX_DESC_REUSE_MASK 0x00040000
#define PB_BUF_REUSE_OFFSET 17
#define PB_BUF_REUSE_MASK 0x00020000
#define LIST_END_OFFSET 16
#define LIST_END_MASK 0x00010000
#define LIST_START_OFFSET 15
#define LIST_START_MASK 0x00008000
#define KEY_IDX_OFFSET 10
#define KEY_IDX_MASK 0x00007C00
#define KEY_TABLE_IDX_OFFSET 8
#define KEY_TABLE_IDX_MASK 0x00000300
#define AVLN_IDX_OFFSET 5
#define AVLN_IDX_MASK 0x000000E0
#define HW_RETRY_CNT_OFFSET 2
#define HW_RETRY_CNT_MASK 0x0000001C
#define CTS_ENABLE_OFFSET 1
#define CTS_ENABLE_MASK 0x00000002
#define RTS_ENABLE_OFFSET 0
#define RTS_ENABLE_MASK 0x00000001

//-----------------------------------
#define CFG_START_WORD13_ADDR 0x0034
#define HP10_FC_OFFSET 0
#define HP10_FC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_END_WORD0_ADDR 0x0000
#define SACK_BITMAP_OFFSET 16
#define SACK_BITMAP_MASK 0xFFFF0000
#define TOTAL_RETRY_CNT_OFFSET 13
#define TOTAL_RETRY_CNT_MASK 0x0000E000
#define MAC_EVENT_ID_OFFSET 9
#define MAC_EVENT_ID_MASK 0x00001E00
#define IS_MACERR_OFFSET 8
#define IS_MACERR_MASK 0x00000100
#define IS_FILTERED_OFFSET 7
#define IS_FILTERED_MASK 0x00000080
#define PHYERR_ID_OFFSET 3
#define PHYERR_ID_MASK 0x00000078
#define IS_PHYERR_OFFSET 2
#define IS_PHYERR_MASK 0x00000004
#define TX_OK_OFFSET 1
#define TX_OK_MASK 0x00000002
#define TX_DONE_OFFSET 0
#define TX_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_END_WORD1_ADDR 0x0004
#define FIRST_TRY_TS_OFFSET 0
#define FIRST_TRY_TS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_END_WORD2_ADDR 0x0008
#define TRY0_RESV_OFFSET 28
#define TRY0_RESV_MASK 0xF0000000
#define TRY0_TX_PACKET_OFFSET 27
#define TRY0_TX_PACKET_MASK 0x08000000
#define TRY0_TX_RTSCTS_OFFSET 26
#define TRY0_TX_RTSCTS_MASK 0x04000000
#define TRY0_RETRY_TIME_OFFSET_OFFSET 0
#define TRY0_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD3_ADDR 0x000C
#define TRY1_RESV_OFFSET 28
#define TRY1_RESV_MASK 0xF0000000
#define TRY1_TX_PACKET_OFFSET 27
#define TRY1_TX_PACKET_MASK 0x08000000
#define TRY1_TX_RTSCTS_OFFSET 26
#define TRY1_TX_RTSCTS_MASK 0x04000000
#define TRY1_RETRY_TIME_OFFSET_OFFSET 0
#define TRY1_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD4_ADDR 0x0010
#define TRY2_RESV_OFFSET 28
#define TRY2_RESV_MASK 0xF0000000
#define TRY2_TX_PACKET_OFFSET 27
#define TRY2_TX_PACKET_MASK 0x08000000
#define TRY2_TX_RTSCTS_OFFSET 26
#define TRY2_TX_RTSCTS_MASK 0x04000000
#define TRY2_RETRY_TIME_OFFSET_OFFSET 0
#define TRY2_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD5_ADDR 0x0014
#define TRY3_RESV_OFFSET 28
#define TRY3_RESV_MASK 0xF0000000
#define TRY3_TX_PACKET_OFFSET 27
#define TRY3_TX_PACKET_MASK 0x08000000
#define TRY3_TX_RTSCTS_OFFSET 26
#define TRY3_TX_RTSCTS_MASK 0x04000000
#define TRY3_RETRY_TIME_OFFSET_OFFSET 0
#define TRY3_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD6_ADDR 0x0018
#define TRY4_RESV_OFFSET 28
#define TRY4_RESV_MASK 0xF0000000
#define TRY4_TX_PACKET_OFFSET 27
#define TRY4_TX_PACKET_MASK 0x08000000
#define TRY4_TX_RTSCTS_OFFSET 26
#define TRY4_TX_RTSCTS_MASK 0x04000000
#define TRY4_RETRY_TIME_OFFSET_OFFSET 0
#define TRY4_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD7_ADDR 0x001C
#define TRY5_RESV_OFFSET 28
#define TRY5_RESV_MASK 0xF0000000
#define TRY5_TX_PACKET_OFFSET 27
#define TRY5_TX_PACKET_MASK 0x08000000
#define TRY5_TX_RTSCTS_OFFSET 26
#define TRY5_TX_RTSCTS_MASK 0x04000000
#define TRY5_RETRY_TIME_OFFSET_OFFSET 0
#define TRY5_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD8_ADDR 0x0020
#define TRY6_RESV_OFFSET 28
#define TRY6_RESV_MASK 0xF0000000
#define TRY6_TX_PACKET_OFFSET 27
#define TRY6_TX_PACKET_MASK 0x08000000
#define TRY6_TX_RTSCTS_OFFSET 26
#define TRY6_TX_RTSCTS_MASK 0x04000000
#define TRY6_RETRY_TIME_OFFSET_OFFSET 0
#define TRY6_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD9_ADDR 0x0024
#define TRY7_RESV_OFFSET 28
#define TRY7_RESV_MASK 0xF0000000
#define TRY7_TX_PACKET_OFFSET 27
#define TRY7_TX_PACKET_MASK 0x08000000
#define TRY7_TX_RTSCTS_OFFSET 26
#define TRY7_TX_RTSCTS_MASK 0x04000000
#define TRY7_RETRY_TIME_OFFSET_OFFSET 0
#define TRY7_RETRY_TIME_OFFSET_MASK 0x03FFFFFF

//-----------------------------------
#define CFG_END_WORD10_ADDR 0x0028
#define SACK_TIMESTAMP_OFFSET 0
#define SACK_TIMESTAMP_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_END_WORD11_ADDR 0x002C
#define PB3_STATUS_OFFSET 24
#define PB3_STATUS_MASK 0xFF000000
#define PB2_STATUS_OFFSET 16
#define PB2_STATUS_MASK 0x00FF0000
#define PB1_STATUS_OFFSET 8
#define PB1_STATUS_MASK 0x0000FF00
#define PB0_STATUS_OFFSET 0
#define PB0_STATUS_MASK 0x000000FF

//-----------------------------------
#define CFG_END_WORD12_ADDR 0x0030
#define TX_FRAME_CUR_PTR_OFFSET 0
#define TX_FRAME_CUR_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_END_WORD13_ADDR 0x0034
#define TX_FRAME_OFFSET_OFFSET 16
#define TX_FRAME_OFFSET_MASK 0xFFFF0000
#define TX_FRAME_BYTE_OFFSET 0
#define TX_FRAME_BYTE_MASK 0x0000FFFF

//-----------------------------------
#define CFG_END_WORD14_ADDR 0x0038
#define TXWINDSZ_OFFSET 28
#define TXWINDSZ_MASK 0xF0000000
#define OLDEST_PB_TRY_NUMBER_OFFSET 24
#define OLDEST_PB_TRY_NUMBER_MASK 0x0F000000
#define MINTXSSN_OFFSET 8
#define MINTXSSN_MASK 0x00FFFF00
#define PB_STATUS_OFFSET 0
#define PB_STATUS_MASK 0x000000FF

//-----------------------------------
#define CFG_END_WORD15_ADDR 0x003C
#define RESV_OFFSET 4
#define RESV_MASK 0xFFFFFFF0
#define MFSCMD_STATE_OFFSET 0
#define MFSCMD_STATE_MASK 0x0000000F

//-----------------------------------
#define CFG_TX_PB_START_0_ADDR 0x0000
#define NEXT_PB_OFFSET 0
#define NEXT_PB_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_TX_PB_START_1_ADDR 0x0004
#define PB_BUF_ADDR_OFFSET 0
#define PB_BUF_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_TX_PB_START_2_ADDR 0x0008
#define SOF_PB_HEADER_OFFSET 0
#define SOF_PB_HEADER_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_TX_PB_START_3_ADDR 0x000c
#define PB_CRC_OFFSET 0
#define PB_CRC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_TX_DUMMY_0_ADDR 0x0000
#define DUMMY_RESRV0_OFFSET 2
#define DUMMY_RESRV0_MASK 0xFFFFFFFC
#define DESC_TYPE_OFFSET 0
#define DESC_TYPE_MASK 0x00000003

//-----------------------------------
#define CFG_TX_DUMMY_1_ADDR 0x0004
#define DUMMY_RESRV1_OFFSET 1
#define DUMMY_RESRV1_MASK 0xFFFFFFFE
#define TX_DONE_OFFSET 0
#define TX_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_TX_DUMMY_2_ADDR 0x0008
#define DUMMY_NEXT_OFFSET 0
#define DUMMY_NEXT_MASK 0xFFFFFFFF

//HW module read/write macro
#define RGF_MAC_TX_DESC_READ_REG(addr) SOC_READ_REG(RGF_MAC_TX_DESC_BASEADDR + addr)
#define RGF_MAC_TX_DESC_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_MAC_TX_DESC_BASEADDR + addr,value)