51 lines
1.6 KiB
C
51 lines
1.6 KiB
C
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//-----------------------------------
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#define CFG_SEC_RVER_ADDR 0x0000
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#define SEC_RF_VER_OFFSET 0
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#define SEC_RF_VER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SEC_GLB_ENA_ADDR 0x0004
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#define RV5_CORE1_EB_OFFSET 6
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#define RV5_CORE1_EB_MASK 0x00000040
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#define INTC1_EB_OFFSET 5
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#define INTC1_EB_MASK 0x00000020
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#define WDG1_EB_OFFSET 4
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#define WDG1_EB_MASK 0x00000010
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#define GTMR1_EB_OFFSET 3
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#define GTMR1_EB_MASK 0x00000008
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#define EFUSE_EB_OFFSET 2
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#define EFUSE_EB_MASK 0x00000004
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#define SEC_EB_OFFSET 1
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#define SEC_EB_MASK 0x00000002
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#define EMC_EB_OFFSET 0
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#define EMC_EB_MASK 0x00000001
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//-----------------------------------
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#define CFG_SEC_GLB_RST_ADDR 0x0008
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#define CHIP_SOFT_RST_OFFSET 7
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#define CHIP_SOFT_RST_MASK 0x00000080
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#define RV5_CORE1_SOFT_RST_P_OFFSET 6
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#define RV5_CORE1_SOFT_RST_P_MASK 0x00000040
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#define INTC1_SOFT_RST_OFFSET 5
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#define INTC1_SOFT_RST_MASK 0x00000020
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#define WDG1_SOFT_RST_OFFSET 4
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#define WDG1_SOFT_RST_MASK 0x00000010
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#define GTMR1_SOFT_RST_OFFSET 3
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#define GTMR1_SOFT_RST_MASK 0x00000008
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#define EFUSE_SOFT_RST_OFFSET 2
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#define EFUSE_SOFT_RST_MASK 0x00000004
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#define SEC_SOFT_RST_OFFSET 1
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#define SEC_SOFT_RST_MASK 0x00000002
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#define EMC_SOFT_RST_OFFSET 0
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#define EMC_SOFT_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_CPU1_START_PC_ADDR 0x004c
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#define CORE1_START_PC_OFFSET 0
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#define CORE1_START_PC_MASK 0xFFFFFFFF
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//HW module read/write macro
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#define SEC_GLB_RF_READ_REG(addr) SOC_READ_REG(SEC_GLB_RF_BASEADDR + addr)
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#define SEC_GLB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SEC_GLB_RF_BASEADDR + addr,value)
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