335 lines
12 KiB
C
335 lines
12 KiB
C
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//-----------------------------------
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#define CFG_PDMA_CONF0_ADDR 0x0
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#define REG_DEV_RX_BRK_EOF_EN_OFFSET 18
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#define REG_DEV_RX_BRK_EOF_EN_MASK 0x00040000
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#define REG_CLK_EN_OFFSET 17
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#define REG_CLK_EN_MASK 0x00020000
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#define REG_MEM_TRANS_EN_OFFSET 15
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#define REG_MEM_TRANS_EN_MASK 0x00008000
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#define REG_OUT_DATA_BURST_EN_OFFSET 14
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#define REG_OUT_DATA_BURST_EN_MASK 0x00004000
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#define REG_INDSCR_BURST_EN_OFFSET 13
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#define REG_INDSCR_BURST_EN_MASK 0x00002000
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#define REG_OUTDSCR_BURST_EN_OFFSET 12
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#define REG_OUTDSCR_BURST_EN_MASK 0x00001000
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#define REG_DEV2_CE_OFFSET 11
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#define REG_DEV2_CE_MASK 0x00000800
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#define REG_DEV1_CE_OFFSET 10
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#define REG_DEV1_CE_MASK 0x00000400
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#define REG_DEV0_CE_OFFSET 9
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#define REG_DEV0_CE_MASK 0x00000200
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#define REG_OUT_EOF_MODE_OFFSET 8
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#define REG_OUT_EOF_MODE_MASK 0x00000100
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#define REG_LOOP_BACK_MODE_OFFSET 7
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#define REG_LOOP_BACK_MODE_MASK 0x00000080
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#define REG_OUT_AUTO_WRBACK_OFFSET 6
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#define REG_OUT_AUTO_WRBACK_MASK 0x00000040
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#define REG_OUT_LOOP_TEST_OFFSET 5
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#define REG_OUT_LOOP_TEST_MASK 0x00000020
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#define REG_IN_LOOP_TEST_OFFSET 4
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#define REG_IN_LOOP_TEST_MASK 0x00000010
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#define REG_AHBM_RST_OFFSET 3
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#define REG_AHBM_RST_MASK 0x00000008
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#define REG_AHBM_FIFO_RST_OFFSET 2
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#define REG_AHBM_FIFO_RST_MASK 0x00000004
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#define REG_OUT_RST_OFFSET 1
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#define REG_OUT_RST_MASK 0x00000002
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#define REG_IN_RST_OFFSET 0
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#define REG_IN_RST_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_INT_RAW_ADDR 0x4
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#define DMA_INFIFO_FULL_WM_INT_RAW_OFFSET 9
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#define DMA_INFIFO_FULL_WM_INT_RAW_MASK 0x00000200
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#define DMA_OUT_TOTAL_EOF_INT_RAW_OFFSET 8
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#define DMA_OUT_TOTAL_EOF_INT_RAW_MASK 0x00000100
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#define DMA_IN_DSCR_EMPTY_INT_RAW_OFFSET 7
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#define DMA_IN_DSCR_EMPTY_INT_RAW_MASK 0x00000080
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#define DMA_OUT_DSCR_ERR_INT_RAW_OFFSET 6
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#define DMA_OUT_DSCR_ERR_INT_RAW_MASK 0x00000040
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#define DMA_IN_DSCR_ERR_INT_RAW_OFFSET 5
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#define DMA_IN_DSCR_ERR_INT_RAW_MASK 0x00000020
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#define DMA_OUT_EOF_INT_RAW_OFFSET 4
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#define DMA_OUT_EOF_INT_RAW_MASK 0x00000010
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#define DMA_OUT_DONE_INT_RAW_OFFSET 3
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#define DMA_OUT_DONE_INT_RAW_MASK 0x00000008
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#define DMA_IN_ERR_EOF_INT_RAW_OFFSET 2
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#define DMA_IN_ERR_EOF_INT_RAW_MASK 0x00000004
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#define DMA_IN_SUC_EOF_INT_RAW_OFFSET 1
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#define DMA_IN_SUC_EOF_INT_RAW_MASK 0x00000002
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#define DMA_IN_DONE_INT_RAW_OFFSET 0
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#define DMA_IN_DONE_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_INT_ST_ADDR 0x8
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#define DMA_INFIFO_FULL_WM_INT_ST_OFFSET 9
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#define DMA_INFIFO_FULL_WM_INT_ST_MASK 0x00000200
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#define DMA_OUT_TOTAL_EOF_INT_ST_OFFSET 8
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#define DMA_OUT_TOTAL_EOF_INT_ST_MASK 0x00000100
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#define DMA_IN_DSCR_EMPTY_INT_ST_OFFSET 7
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#define DMA_IN_DSCR_EMPTY_INT_ST_MASK 0x00000080
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#define DMA_OUT_DSCR_ERR_INT_ST_OFFSET 6
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#define DMA_OUT_DSCR_ERR_INT_ST_MASK 0x00000040
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#define DMA_IN_DSCR_ERR_INT_ST_OFFSET 5
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#define DMA_IN_DSCR_ERR_INT_ST_MASK 0x00000020
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#define DMA_OUT_EOF_INT_ST_OFFSET 4
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#define DMA_OUT_EOF_INT_ST_MASK 0x00000010
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#define DMA_OUT_DONE_INT_ST_OFFSET 3
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#define DMA_OUT_DONE_INT_ST_MASK 0x00000008
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#define DMA_IN_ERR_EOF_INT_ST_OFFSET 2
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#define DMA_IN_ERR_EOF_INT_ST_MASK 0x00000004
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#define DMA_IN_SUC_EOF_INT_ST_OFFSET 1
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#define DMA_IN_SUC_EOF_INT_ST_MASK 0x00000002
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#define DMA_IN_DONE_INT_ST_OFFSET 0
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#define DMA_IN_DONE_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_INT_ENA_ADDR 0xC
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#define DMA_INFIFO_FULL_WM_INT_ENA_OFFSET 9
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#define DMA_INFIFO_FULL_WM_INT_ENA_MASK 0x00000200
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#define DMA_OUT_TOTAL_EOF_INT_ENA_OFFSET 8
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#define DMA_OUT_TOTAL_EOF_INT_ENA_MASK 0x00000100
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#define DMA_IN_DSCR_EMPTY_INT_ENA_OFFSET 7
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#define DMA_IN_DSCR_EMPTY_INT_ENA_MASK 0x00000080
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#define DMA_OUT_DSCR_ERR_INT_ENA_OFFSET 6
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#define DMA_OUT_DSCR_ERR_INT_ENA_MASK 0x00000040
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#define DMA_IN_DSCR_ERR_INT_ENA_OFFSET 5
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#define DMA_IN_DSCR_ERR_INT_ENA_MASK 0x00000020
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#define DMA_OUT_EOF_INT_ENA_OFFSET 4
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#define DMA_OUT_EOF_INT_ENA_MASK 0x00000010
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#define DMA_OUT_DONE_INT_ENA_OFFSET 3
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#define DMA_OUT_DONE_INT_ENA_MASK 0x00000008
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#define DMA_IN_ERR_EOF_INT_ENA_OFFSET 2
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#define DMA_IN_ERR_EOF_INT_ENA_MASK 0x00000004
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#define DMA_IN_SUC_EOF_INT_ENA_OFFSET 1
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#define DMA_IN_SUC_EOF_INT_ENA_MASK 0x00000002
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#define DMA_IN_DONE_INT_ENA_OFFSET 0
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#define DMA_IN_DONE_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_INT_CLR_ADDR 0x10
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#define REG_DMA_INFIFO_FULL_WM_INT_CLR_OFFSET 9
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#define REG_DMA_INFIFO_FULL_WM_INT_CLR_MASK 0x00000200
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#define REG_OUT_TOTAL_EOF_INT_CLR_OFFSET 8
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#define REG_OUT_TOTAL_EOF_INT_CLR_MASK 0x00000100
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#define REG_IN_DSCR_EMPTY_INT_CLR_OFFSET 7
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#define REG_IN_DSCR_EMPTY_INT_CLR_MASK 0x00000080
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#define REG_OUT_DSCR_ERR_INT_CLR_OFFSET 6
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#define REG_OUT_DSCR_ERR_INT_CLR_MASK 0x00000040
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#define REG_IN_DSCR_ERR_INT_CLR_OFFSET 5
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#define REG_IN_DSCR_ERR_INT_CLR_MASK 0x00000020
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#define REG_OUT_EOF_INT_CLR_OFFSET 4
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#define REG_OUT_EOF_INT_CLR_MASK 0x00000010
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#define REG_OUT_DONE_INT_CLR_OFFSET 3
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#define REG_OUT_DONE_INT_CLR_MASK 0x00000008
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#define REG_IN_ERR_EOF_INT_CLR_OFFSET 2
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#define REG_IN_ERR_EOF_INT_CLR_MASK 0x00000004
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#define REG_IN_SUC_EOF_INT_CLR_OFFSET 1
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#define REG_IN_SUC_EOF_INT_CLR_MASK 0x00000002
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#define REG_IN_DONE_INT_CLR_OFFSET 0
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#define REG_IN_DONE_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_OUT_STATUS_ADDR 0x14
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#define OUT_EMPTY_OFFSET 1
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#define OUT_EMPTY_MASK 0x00000002
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#define OUT_FULL_OFFSET 0
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#define OUT_FULL_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_OUT_PUSH_ADDR 0x18
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#define REG_OUTFIFO_PUSH_OFFSET 16
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#define REG_OUTFIFO_PUSH_MASK 0x00010000
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#define REG_OUTFIFO_WDATA_OFFSET 0
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#define REG_OUTFIFO_WDATA_MASK 0x000001FF
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//-----------------------------------
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#define CFG_PDMA_IN_STATUS_ADDR 0x1C
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#define DMA_RX_ERR_CAUSE_OFFSET 4
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#define DMA_RX_ERR_CAUSE_MASK 0x00000070
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#define IN_EMPTY_OFFSET 1
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#define IN_EMPTY_MASK 0x00000002
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#define IN_FULL_OFFSET 0
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#define IN_FULL_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_IN_POP_ADDR 0x20
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#define REG_INFIFO_POP_OFFSET 16
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#define REG_INFIFO_POP_MASK 0x00010000
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#define REG_INFIFO_RDATA_OFFSET 0
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#define REG_INFIFO_RDATA_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_PDMA_OUT_LINK_ADDR 0x24
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#define REG_OUTLINK_RESTART_OFFSET 30
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#define REG_OUTLINK_RESTART_MASK 0x40000000
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#define REG_OUTLINK_START_OFFSET 29
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#define REG_OUTLINK_START_MASK 0x20000000
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#define REG_OUTLINK_STOP_OFFSET 28
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#define REG_OUTLINK_STOP_MASK 0x10000000
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#define REG_OUTLINK_ADDR_OFFSET 0
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#define REG_OUTLINK_ADDR_MASK 0x0FFFFFFF
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//-----------------------------------
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#define CFG_PDMA_IN_LINK_ADDR 0x28
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#define REG_INLINK_AUTO_RET_OFFSET 31
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#define REG_INLINK_AUTO_RET_MASK 0x80000000
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#define REG_INLINK_RESTART_OFFSET 30
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#define REG_INLINK_RESTART_MASK 0x40000000
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#define REG_INLINK_START_OFFSET 29
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#define REG_INLINK_START_MASK 0x20000000
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#define REG_INLINK_STOP_OFFSET 28
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#define REG_INLINK_STOP_MASK 0x10000000
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#define REG_INLINK_ADDR_OFFSET 0
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#define REG_INLINK_ADDR_MASK 0x0FFFFFFF
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//-----------------------------------
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#define CFG_PDMA_CONF1_ADDR 0x2C
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#define REG_DMA_INFIFO_FULL_THRS_OFFSET 8
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#define REG_DMA_INFIFO_FULL_THRS_MASK 0x000FFF00
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#define REG_CHECK_OWNER_OFFSET 1
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#define REG_CHECK_OWNER_MASK 0x00000002
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#define REG_CRC_DISABLE_OFFSET 0
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#define REG_CRC_DISABLE_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_STATE0_ADDR 0x30
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#define DMA_STATE0_OFFSET 0
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#define DMA_STATE0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_STATE1_ADDR 0x34
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#define DMA_STATE1_OFFSET 0
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#define DMA_STATE1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_OUT_EOF_DES_ADDR_ADDR 0x38
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#define OUT_EOF_DES_ADDR_OFFSET 0
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#define OUT_EOF_DES_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_IN_SUC_EOF_DES_ADDR_ADDR 0x3C
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#define IN_SUC_EOF_DES_ADDR_OFFSET 0
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#define IN_SUC_EOF_DES_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_IN_ERR_EOF_DES_ADDR_ADDR 0x40
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#define IN_ERR_EOF_DES_ADDR_OFFSET 0
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#define IN_ERR_EOF_DES_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_OUT_EOF_BFR_DES_ADDR_ADDR 0x44
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#define OUT_EOF_BFR_DES_ADDR_OFFSET 0
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#define OUT_EOF_BFR_DES_ADDR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_AHB_TEST_ADDR 0x48
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#define REG_AHB_TESTADDR_OFFSET 4
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#define REG_AHB_TESTADDR_MASK 0x00000030
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#define REG_AHB_TESTMODE_OFFSET 0
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#define REG_AHB_TESTMODE_MASK 0x00000007
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//-----------------------------------
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#define CFG_PDMA_IN_DSCR_ADDR 0x4C
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#define INLINK_DSCR_OFFSET 0
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#define INLINK_DSCR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_IN_DSCR_BF0_ADDR 0x50
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#define INLINK_DSCR_BF0_OFFSET 0
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#define INLINK_DSCR_BF0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_IN_DSCR_BF1_ADDR 0x54
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#define INLINK_DSCR_BF1_OFFSET 0
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#define INLINK_DSCR_BF1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_OUT_DSCR_ADDR 0x58
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#define OUTLINK_DSCR_OFFSET 0
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#define OUTLINK_DSCR_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_OUT_DSCR_BF0_ADDR 0x5C
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#define OUTLINK_DSCR_BF0_OFFSET 0
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#define OUTLINK_DSCR_BF0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_OUT_DSCR_BF1_ADDR 0x60
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#define OUTLINK_DSCR_BF1_OFFSET 0
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#define OUTLINK_DSCR_BF1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_CRC_CFG0_ADDR 0x64
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#define CRC_OUT_DONE_OFFSET 9
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#define CRC_OUT_DONE_MASK 0x00000200
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#define CRC_ENA_OFFSET 8
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#define CRC_ENA_MASK 0x00000100
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#define CRC_MODE_OFFSET 0
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#define CRC_MODE_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PDMA_CRC_CFG1_ADDR 0x68
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#define CRC_OUT_OFFSET 0
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#define CRC_OUT_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_CRC_OUT_ADDR 0x6C
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#define CRC_POLYNOMIAL_OFFSET 0
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#define CRC_POLYNOMIAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PDMA_LINK_ST_ADDR 0x70
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#define DMA_OUTLINK_PARK_OFFSET 1
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#define DMA_OUTLINK_PARK_MASK 0x00000002
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#define DMA_INLINK_PARK_OFFSET 0
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#define DMA_INLINK_PARK_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_CRC_INI_ADDR 0x74
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#define CRC_INIT_OFFSET 0
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#define CRC_INIT_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_CKSUM_INI_ADDR 0x78
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#define CKSUM_INIT_OFFSET 0
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#define CKSUM_INIT_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDMA_CKSUM_CFG_ADDR 0x7C
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#define CKSUM_OUT_OFFSET 16
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#define CKSUM_OUT_MASK 0xFFFF0000
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#define CKSUM_ENA_OFFSET 0
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#define CKSUM_ENA_MASK 0x00000001
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//HW module read/write macro
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#define DMA_READ_REG(addr) SOC_READ_REG(DMA_BASEADDR + addr)
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#define DMA_WRITE_REG(addr,value) SOC_WRITE_REG(DMA_BASEADDR + addr,value)
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#define DMA1_READ_REG(addr) SOC_READ_REG(DMA1_BASEADDR + addr)
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#define DMA1_WRITE_REG(addr,value) SOC_WRITE_REG(DMA1_BASEADDR + addr,value)
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#define DMA2_READ_REG(addr) SOC_READ_REG(DMA2_BASEADDR + addr)
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#define DMA2_WRITE_REG(addr,value) SOC_WRITE_REG(DMA2_BASEADDR + addr,value)
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#define DMA3_READ_REG(addr) SOC_READ_REG(DMA3_BASEADDR + addr)
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#define DMA3_WRITE_REG(addr,value) SOC_WRITE_REG(DMA3_BASEADDR + addr,value)
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#define DMA4_READ_REG(addr) SOC_READ_REG(DMA4_BASEADDR + addr)
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#define DMA4_WRITE_REG(addr,value) SOC_WRITE_REG(DMA4_BASEADDR + addr,value)
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#define DMA5_READ_REG(addr) SOC_READ_REG(DMA5_BASEADDR + addr)
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#define DMA5_WRITE_REG(addr,value) SOC_WRITE_REG(DMA5_BASEADDR + addr,value)
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#define DMA6_READ_REG(addr) SOC_READ_REG(DMA6_BASEADDR + addr)
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#define DMA6_WRITE_REG(addr,value) SOC_WRITE_REG(DMA6_BASEADDR + addr,value)
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#define DMA7_READ_REG(addr) SOC_READ_REG(DMA7_BASEADDR + addr)
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#define DMA7_WRITE_REG(addr,value) SOC_WRITE_REG(DMA7_BASEADDR + addr,value)
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#define DMA8_READ_REG(addr) SOC_READ_REG(DMA8_BASEADDR + addr)
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#define DMA8_WRITE_REG(addr,value) SOC_WRITE_REG(DMA8_BASEADDR + addr,value)
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#define DMA9_READ_REG(addr) SOC_READ_REG(DMA9_BASEADDR + addr)
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#define DMA9_WRITE_REG(addr,value) SOC_WRITE_REG(DMA9_BASEADDR + addr,value)
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#define DMA10_READ_REG(addr) SOC_READ_REG(DMA10_BASEADDR + addr)
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#define DMA10_WRITE_REG(addr,value) SOC_WRITE_REG(DMA10_BASEADDR + addr,value)
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#define SW_DMA0_READ_REG(addr) SOC_READ_REG(SW_DMA_REG0_BASEADDR + addr)
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#define SW_DMA0_WRITE_REG(addr,value) \
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SOC_WRITE_REG(SW_DMA_REG0_BASEADDR + addr,value)
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#define SW_DMA1_READ_REG(addr) SOC_READ_REG(SW_DMA_REG1_BASEADDR + addr)
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#define SW_DMA1_WRITE_REG(addr,value) \
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SOC_WRITE_REG(SW_DMA_REG1_BASEADDR + addr,value)
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