kunlun/inc/hw/reg/riscv/15/sadc_reg.h

//-----------------------------------
#define CFG_SADC_RVER_ADDR 0x0000
#define SADC_RF_VER_OFFSET 0
#define SADC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SADC_CFG0_ADDR 0x0004
#define SEL_MUX_DLY_NUM_OFFSET 10
#define SEL_MUX_DLY_NUM_MASK 0x00003C00
#define SADC_PHASE_SEL_OFFSET 8
#define SADC_PHASE_SEL_MASK 0x00000300
#define SADC_DATA_NUM_OFFSET 1
#define SADC_DATA_NUM_MASK 0x000000FE
#define SADC_STOP_OFFSET 0
#define SADC_STOP_MASK 0x00000001

//-----------------------------------
#define CFG_SADC_CFG1_ADDR 0x0008
#define SADC_PHASE_SW_MAX_OFFSET 3
#define SADC_PHASE_SW_MAX_MASK 0x000007F8
#define SADC_TX_CHL_SEL_OFFSET 1
#define SADC_TX_CHL_SEL_MASK 0x00000006
#define SADC_PHASE_MODE_OFFSET 0
#define SADC_PHASE_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_SADC_GAIN_CFG0_ADDR 0x000C
#define ADC3_GAIN_OFFSET 18
#define ADC3_GAIN_MASK 0x00FC0000
#define ADC2_GAIN_OFFSET 12
#define ADC2_GAIN_MASK 0x0003F000
#define ADC1_GAIN_OFFSET 6
#define ADC1_GAIN_MASK 0x00000FC0
#define ADC0_GAIN_OFFSET 0
#define ADC0_GAIN_MASK 0x0000003F

//-----------------------------------
#define CFG_SADC_GAIN_CFG1_ADDR 0x0010
#define ADC0_1_GAIN_OFFSET 18
#define ADC0_1_GAIN_MASK 0x00FC0000
#define ADC2_3_GAIN_OFFSET 12
#define ADC2_3_GAIN_MASK 0x0003F000
#define ADC5_GAIN_OFFSET 6
#define ADC5_GAIN_MASK 0x00000FC0
#define ADC4_GAIN_OFFSET 0
#define ADC4_GAIN_MASK 0x0000003F

//-----------------------------------
#define CFG_SADC_PHASE_SEL_ADDR 0x0014
#define PHASE3_DATAIN_INV_OFFSET 19
#define PHASE3_DATAIN_INV_MASK 0x00080000
#define PHASE2_DATAIN_INV_OFFSET 18
#define PHASE2_DATAIN_INV_MASK 0x00040000
#define PHASE1_DATAIN_INV_OFFSET 17
#define PHASE1_DATAIN_INV_MASK 0x00020000
#define PHASE0_DATAIN_INV_OFFSET 16
#define PHASE0_DATAIN_INV_MASK 0x00010000
#define PHASE3_SEL_SCL_MUX_OFFSET 12
#define PHASE3_SEL_SCL_MUX_MASK 0x0000F000
#define PHASE2_SEL_SCL_MUX_OFFSET 8
#define PHASE2_SEL_SCL_MUX_MASK 0x00000F00
#define PHASE1_SEL_SCL_MUX_OFFSET 4
#define PHASE1_SEL_SCL_MUX_MASK 0x000000F0
#define PHASE0_SEL_SCL_MUX_OFFSET 0
#define PHASE0_SEL_SCL_MUX_MASK 0x0000000F

//-----------------------------------
#define CFG_SADC_DC_THR_ADDR 0x0018
#define I2S_NEED_SUB_DC_THR_OFFSET 15
#define I2S_NEED_SUB_DC_THR_MASK 0x00008000
#define DMA_NEED_SUB_DC_THR_OFFSET 14
#define DMA_NEED_SUB_DC_THR_MASK 0x00004000
#define SADC_DC_THR_OFFSET 0
#define SADC_DC_THR_MASK 0x00003FFF

//-----------------------------------
#define CFG_SADC_SUM_ADDR 0x001C
#define SADC_SUM_CLR_OFFSET 17
#define SADC_SUM_CLR_MASK 0x00020000
#define SADC_SUM_VLD_OFFSET 16
#define SADC_SUM_VLD_MASK 0x00010000
#define SADC_SUM_OFFSET 0
#define SADC_SUM_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SADC_RX_NUM_ADDR 0x0020
#define SADC_RX_EOF_NUM_OFFSET 0
#define SADC_RX_EOF_NUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SADC_RX_STATUS_ADDR 0x0024
#define SADC_RX_EOF_OFFSET 0
#define SADC_RX_EOF_MASK 0x00000001

//-----------------------------------
#define CFG_SADC_CLR_ADDR 0x0028
#define SADC_RX_EOF_CLR_OFFSET 0
#define SADC_RX_EOF_CLR_MASK 0x00000001

//HW module read/write macro
#define SADC_READ_REG(addr) SOC_READ_REG(SADC_BASEADDR + addr)
#define SADC_WRITE_REG(addr,value) SOC_WRITE_REG(SADC_BASEADDR + addr,value)