kunlun/inc/hw/reg/riscv2/15/phy_ana_reg.h

//-----------------------------------
#define CFG_BB_ANA_TOP_ADDR 0x0000
#define SW_ADC_RESET_N_OFFSET 7
#define SW_ADC_RESET_N_MASK 0x00000080
#define SW_ADC_EN_OFFSET 6
#define SW_ADC_EN_MASK 0x00000040
#define SW_RX_FE_EN_OFFSET 5
#define SW_RX_FE_EN_MASK 0x00000020
#define SW_ENLIC_RX_OFFSET 4
#define SW_ENLIC_RX_MASK 0x00000010
#define SW_TX_DAC_EN_OFFSET 2
#define SW_TX_DAC_EN_MASK 0x00000004
#define SW_TX_EN_OFFSET 1
#define SW_TX_EN_MASK 0x00000002
#define SW_ENLIC_TX_OFFSET 0
#define SW_ENLIC_TX_MASK 0x00000001

//-----------------------------------
#define CFG_BB_ANA_RX_GAIN_ADDR 0x0004
#define SW_RX_GLNA_OFFSET 29
#define SW_RX_GLNA_MASK 0xE0000000
#define SW_RX_BQ_QVALUE_OFFSET 23
#define SW_RX_BQ_QVALUE_MASK 0x1F800000
#define SW_RX_FE_BYPHPF_OFFSET 22
#define SW_RX_FE_BYPHPF_MASK 0x00400000
#define SW_RX_FE_HPFENORD2_OFFSET 21
#define SW_RX_FE_HPFENORD2_MASK 0x00200000
#define SW_RX_FE_PGAOFFSET_OFFSET 16
#define SW_RX_FE_PGAOFFSET_MASK 0x001F0000
#define SW_RX_FE_PGFOFFSET_OFFSET 10
#define SW_RX_FE_PGFOFFSET_MASK 0x0000FC00
#define SW_RX_FE_GPGA_OFFSET 6
#define SW_RX_FE_GPGA_MASK 0x000003C0
#define SW_RX_FE_GBQ_OFFSET 3
#define SW_RX_FE_GBQ_MASK 0x00000038
#define SW_RX_FE_GPGF_OFFSET 0
#define SW_RX_FE_GPGF_MASK 0x00000007

//-----------------------------------
#define CFG_BB_ANA_TX_GAIN_ADDR 0x0008
#define SW_TX_SELC_PGA_OFFSET 3
#define SW_TX_SELC_PGA_MASK 0x00000038
#define SW_TX_GPGA_OFFSET 0
#define SW_TX_GPGA_MASK 0x00000007

//-----------------------------------
#define CFG_BB_ANA_TX_CFG_0_ADDR 0x000C
#define SW_TX_PGACOMP_OFFSET 31
#define SW_TX_PGACOMP_MASK 0x80000000
#define SW_TX_COMPEN_OFFSET 30
#define SW_TX_COMPEN_MASK 0x40000000
#define SW_TX_PGATESTEN_OFFSET 29
#define SW_TX_PGATESTEN_MASK 0x20000000
#define SW_TX_FLTTESTEN_OFFSET 28
#define SW_TX_FLTTESTEN_MASK 0x10000000
#define SW_TX_TESTEN_OFFSET 27
#define SW_TX_TESTEN_MASK 0x08000000
#define SW_TX_BURNIN_OFFSET 26
#define SW_TX_BURNIN_MASK 0x04000000
#define SW_TX_FULLSCALE_OFFSET 25
#define SW_TX_FULLSCALE_MASK 0x02000000
#define SW_TX_MINSCALE_B_OFFSET 24
#define SW_TX_MINSCALE_B_MASK 0x01000000
#define SW_TX_ATB_SEL_OFFSET 18
#define SW_TX_ATB_SEL_MASK 0x00FC0000
#define SW_TX_DATAOVR_OFFSET 8
#define SW_TX_DATAOVR_MASK 0x0003FF00
#define SW_TX_DATAOVREN_OFFSET 7
#define SW_TX_DATAOVREN_MASK 0x00000080
#define SW_TX_CGMBYP_OFFSET 2
#define SW_TX_CGMBYP_MASK 0x0000007C
#define SW_TX_PWDCGM_OFFSET 1
#define SW_TX_PWDCGM_MASK 0x00000002
#define SW_TX_INVCLKEN_OFFSET 0
#define SW_TX_INVCLKEN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_ANA_RX_CFG_0_ADDR 0x0010
#define SW_RX_FE_PGFLOOPEN_OFFSET 31
#define SW_RX_FE_PGFLOOPEN_MASK 0x80000000
#define SW_RX_FE_IB_PGA_CTRL_OFFSET 27
#define SW_RX_FE_IB_PGA_CTRL_MASK 0x38000000
#define SW_RX_FE_PWDPGFOFFSET_OFFSET 26
#define SW_RX_FE_PWDPGFOFFSET_MASK 0x04000000
#define SW_RX_FE_PWDPGAOFFSET_OFFSET 25
#define SW_RX_FE_PWDPGAOFFSET_MASK 0x02000000
#define SW_RX_FE_PWDCGM_OFFSET 24
#define SW_RX_FE_PWDCGM_MASK 0x01000000
#define SW_RX_FE_CGMBYP_OFFSET 19
#define SW_RX_FE_CGMBYP_MASK 0x00F80000
#define SW_RX_FE_TRIM_BVPC_OFFSET 16
#define SW_RX_FE_TRIM_BVPC_MASK 0x00070000
#define SW_RX_FE_SELC_PGA_OFFSET 12
#define SW_RX_FE_SELC_PGA_MASK 0x00003000
#define SW_RX_FE_SELC_HPF_OFFSET 8
#define SW_RX_FE_SELC_HPF_MASK 0x00000300
#define SW_RX_FE_SELC_PGF_BQ_OFFSET 0
#define SW_RX_FE_SELC_PGF_BQ_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_ANA_RX_CFG_1_ADDR 0x0014
#define SW_RX_FE_ATB_SEL_OFFSET 5
#define SW_RX_FE_ATB_SEL_MASK 0x000003E0
#define SW_RX_FE_PGATESTEN_OFFSET 4
#define SW_RX_FE_PGATESTEN_MASK 0x00000010
#define SW_RX_FE_BQTESTEN_OFFSET 3
#define SW_RX_FE_BQTESTEN_MASK 0x00000008
#define SW_RX_FE_PGFTESTEN_OFFSET 2
#define SW_RX_FE_PGFTESTEN_MASK 0x00000004
#define SW_RX_FE_HPFTESTEN_OFFSET 1
#define SW_RX_FE_HPFTESTEN_MASK 0x00000002
#define SW_RX_FE_TESTEN_OFFSET 0
#define SW_RX_FE_TESTEN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_ANA_RX_ADC_ADDR 0x0018
#define SW_RX_ADC_TIMEOUT_DIG_OFFSET 27
#define SW_RX_ADC_TIMEOUT_DIG_MASK 0x08000000
#define SW_ADC_TIMEOUT_B_PULSE_COUNTER_OFFSET 24
#define SW_ADC_TIMEOUT_B_PULSE_COUNTER_MASK 0x07000000
#define SW_ADC_EOC_DIG_OFFSET 23
#define SW_ADC_EOC_DIG_MASK 0x00800000
#define SW_ADC_EOC_PULSE_COUNTER_OFFSET 20
#define SW_ADC_EOC_PULSE_COUNTER_MASK 0x00700000
#define SW_BG_ADCREF_TRIM_OFFSET 17
#define SW_BG_ADCREF_TRIM_MASK 0x000E0000
#define SW_ADC_F_H_OFFSET 14
#define SW_ADC_F_H_MASK 0x0001C000
#define SW_ADC_CFG_DLY_OFFSET 11
#define SW_ADC_CFG_DLY_MASK 0x00003800
#define SW_ADC_CFG_SAMPLE_CLK_OFFSET 10
#define SW_ADC_CFG_SAMPLE_CLK_MASK 0x00000400
#define SW_RX_ADC_EN_CALIBRATION_COUNTER_OFFSET 9
#define SW_RX_ADC_EN_CALIBRATION_COUNTER_MASK 0x00000200
#define SW_RX_ADC_EN_TIMER_OFFSET 8
#define SW_RX_ADC_EN_TIMER_MASK 0x00000100
#define SW_RX_ADC_TIMER_DLY_OFFSET 4
#define SW_RX_ADC_TIMER_DLY_MASK 0x000000F0
#define SW_RX_ADC_ATB_SEL_OFFSET 1
#define SW_RX_ADC_ATB_SEL_MASK 0x00000006
#define SW_RX_ADC_TESTIN_EN_OFFSET 0
#define SW_RX_ADC_TESTIN_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_ANA_BIAS_IC0_ADDR 0x001C
#define SW_BG_IC25U_ADJ_BIT0_OFFSET 0
#define SW_BG_IC25U_ADJ_BIT0_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_ANA_BIAS_IC1_ADDR 0x0020
#define SW_BG_IC25U_ADJ_BIT1_OFFSET 0
#define SW_BG_IC25U_ADJ_BIT1_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_ANA_BIAS_IR0_ADDR 0x0024
#define SW_BG_IR25U_ADJ_BIT0_OFFSET 0
#define SW_BG_IR25U_ADJ_BIT0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_ANA_BIAS_IR1_ADDR 0x0028
#define SW_BG_IR25U_ADJ_BIT1_OFFSET 0
#define SW_BG_IR25U_ADJ_BIT1_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_ANA_TOP_HWEN_ADDR 0x002C
#define SW_TOP_HW_EN_OFFSET 0
#define SW_TOP_HW_EN_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_ANA_RXGAIN_HWEN_ADDR 0x0030
#define SW_RXGAIN_HW_EN_OFFSET 0
#define SW_RXGAIN_HW_EN_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_ANA_TXGAIN_HWEN_ADDR 0x0034
#define SW_TXGAIN_HW_EN_OFFSET 0
#define SW_TXGAIN_HW_EN_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_ANA_EXT0_HWEN_ADDR 0x0038
#define SW_EXT0_HW_EN_OFFSET 0
#define SW_EXT0_HW_EN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_ANA_EXT1_HWEN_ADDR 0x003C
#define SW_EXT1_HW_EN_OFFSET 0
#define SW_EXT1_HW_EN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_ANA_EXT2_HWEN_ADDR 0x0040
#define SW_EXT2_HW_EN_OFFSET 0
#define SW_EXT2_HW_EN_MASK 0xFFFFFFFF

//HW module read/write macro
#define PHY_ANA_READ_REG(addr) SOC_READ_REG(PHY_ANA_BASEADDR + addr)
#define PHY_ANA_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_ANA_BASEADDR + addr,value)