kunlun/inc/hw/reg/riscv2/15/phy_tx_reg.h

//-----------------------------------
#define CFG_BB_TEST_ONLY_ADDR 0x0000
#define SW_ALWAYS_TX_PREAM_OFFSET 0
#define SW_ALWAYS_TX_PREAM_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_ADDR 0x0004
#define SW_PWR_BACKOFF_16QAM_OFFSET 16
#define SW_PWR_BACKOFF_16QAM_MASK 0x000F0000
#define SW_PWR_BACKOFF_QPSK_OFFSET 12
#define SW_PWR_BACKOFF_QPSK_MASK 0x0000F000

//-----------------------------------
#define CFG_BB_TX_IFFT_CTRL_ADDR 0x0008
#define SW_IFFT_TD_BIT_SEL_OFFSET 0
#define SW_IFFT_TD_BIT_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_BB_TX_TURBO_SET_ADDR 0x000C
#define SW_TX_SCRAMBLE_BASED_PPDU_OFFSET 2
#define SW_TX_SCRAMBLE_BASED_PPDU_MASK 0x00000004
#define SW_TX_SCRAMBLE_RESET_MODE_OFFSET 1
#define SW_TX_SCRAMBLE_RESET_MODE_MASK 0x00000002
#define SW_TX_SCRAMBLE_MODE_OFFSET 0
#define SW_TX_SCRAMBLE_MODE_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_NSG_PREAM_NUM0_ADDR 0x0010
#define SW_OPT_FOR_TONE_MASK_RD_CONVERGENCE_OFFSET 31
#define SW_OPT_FOR_TONE_MASK_RD_CONVERGENCE_MASK 0x80000000
#define SW_FC_SYMB_DONE_DLY_NUM_OFFSET 28
#define SW_FC_SYMB_DONE_DLY_NUM_MASK 0x70000000
#define SW_MAPPING_DONE_DLY_NUM_OFFSET 24
#define SW_MAPPING_DONE_DLY_NUM_MASK 0x0F000000
#define SW_NSG_BMCS_BAND2_PREAM_NUM_OFFSET 16
#define SW_NSG_BMCS_BAND2_PREAM_NUM_MASK 0x00FF0000
#define SW_NSG_BMCS_BAND1_PREAM_NUM_OFFSET 8
#define SW_NSG_BMCS_BAND1_PREAM_NUM_MASK 0x0000FF00
#define SW_NSG_BMCS_BAND0_PREAM_NUM_OFFSET 0
#define SW_NSG_BMCS_BAND0_PREAM_NUM_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_TX_NSG_PREAM_NUM1_ADDR 0x0014
#define SW_NSG_EMCS_BAND2_PREAM_NUM_OFFSET 16
#define SW_NSG_EMCS_BAND2_PREAM_NUM_MASK 0x00FF0000
#define SW_NSG_EMCS_BAND1_PREAM_NUM_OFFSET 8
#define SW_NSG_EMCS_BAND1_PREAM_NUM_MASK 0x0000FF00
#define SW_NSG_EMCS_BAND0_PREAM_NUM_OFFSET 0
#define SW_NSG_EMCS_BAND0_PREAM_NUM_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_TX_MAC_TMI_CTRL_ADDR 0x0018
#define SW_TX_MAC_PB_SIZE_EN_OFFSET 0
#define SW_TX_MAC_PB_SIZE_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR 0x0020
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND0_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND1_ADDR 0x0024
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND1_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE0_BAND2_ADDR 0x0028
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE0_BAND2_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_TX_DLY_ADDR 0x002C
#define SW_TX_DLY_SG_OFFSET 16
#define SW_TX_DLY_SG_MASK 0x0FFF0000
#define SW_TX_DLY_GP_OFFSET 0
#define SW_TX_DLY_GP_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND0_ADDR 0x0030
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND0_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND1_ADDR 0x0034
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND1_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_RATE1_BAND2_ADDR 0x0038
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_RATE1_BAND2_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_DB_AMP_CTRL_SHORT_PREAM_ADDR 0x003c
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_INT_OFFSET 4
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_INT_MASK 0x000007F0
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC_OFFSET 0
#define SW_SHORT_PREAM_DB_UP_AMP_PARA_FRAC_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE0_ADDR 0x0040
#define SW_PHY_TX_SPARE0_OFFSET 0
#define SW_PHY_TX_SPARE0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE1_ADDR 0x0044
#define SW_PHY_TX_SPARE1_OFFSET 0
#define SW_PHY_TX_SPARE1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE2_ADDR 0x0048
#define SW_PHY_TX_SPARE2_OFFSET 0
#define SW_PHY_TX_SPARE2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_PHY_TX_SPARE3_ADDR 0x004c
#define SW_PHY_TX_SPARE3_OFFSET 0
#define SW_PHY_TX_SPARE3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_NSG_PRE_CAL_ADDR 0x0050
#define SW_MINUS_VALUE_OFFSET 1
#define SW_MINUS_VALUE_MASK 0x0000000E
#define SW_FORBID_ONCE_NSG_ROBO_OFFSET 0
#define SW_FORBID_ONCE_NSG_ROBO_MASK 0x00000001

//-----------------------------------
#define CFG_BB_DIVER_ADD_BAND_INTERVAL_ADDR 0x0054
#define SW_DIVERSITY_ADD_BAND_INTERVAL_OFFSET 0
#define SW_DIVERSITY_ADD_BAND_INTERVAL_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_FC_SEND_OVERWR_0_ADDR 0x0060
#define SW_TX_FC_SEND_OVER_WRITE_WORD_0_OFFSET 0
#define SW_TX_FC_SEND_OVER_WRITE_WORD_0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FC_SEND_OVERWR_1_ADDR 0x0064
#define SW_TX_FC_SEND_OVER_WRITE_WORD_1_OFFSET 0
#define SW_TX_FC_SEND_OVER_WRITE_WORD_1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FC_SEND_OVERWR_2_ADDR 0x0068
#define SW_TX_FC_SEND_OVER_WRITE_WORD_2_OFFSET 0
#define SW_TX_FC_SEND_OVER_WRITE_WORD_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FC_SEND_OVERWR_3_ADDR 0x006c
#define SW_TX_FC_SEND_OVER_WRITE_WORD_3_OFFSET 0
#define SW_TX_FC_SEND_OVER_WRITE_WORD_3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FC_SEND_OVERWR_CTRL_ADDR 0x0070
#define SW_TX_FC_SEND_OVER_WRITE_PULSE_OFFSET 0
#define SW_TX_FC_SEND_OVER_WRITE_PULSE_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_TURBO_ENC_PAUSE_CTRL_ADDR 0x0074
#define SW_TURBO_1_ENC_PAUSE_STS_OFFSET 12
#define SW_TURBO_1_ENC_PAUSE_STS_MASK 0x00001000
#define SW_TURBO_1_ENC_PAUSE_PLS_OFFSET 8
#define SW_TURBO_1_ENC_PAUSE_PLS_MASK 0x00000100
#define SW_TURBO_0_ENC_PAUSE_STS_OFFSET 4
#define SW_TURBO_0_ENC_PAUSE_STS_MASK 0x00000010
#define SW_TURBO_0_ENC_PAUSE_PLS_OFFSET 0
#define SW_TURBO_0_ENC_PAUSE_PLS_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_TURBO_0_ENC_PAUSE_NUM_ADDR 0x0078
#define SW_TURBO_0_ENC_PAUSE_NUM_OFFSET 0
#define SW_TURBO_0_ENC_PAUSE_NUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_TURBO_1_ENC_PAUSE_NUM_ADDR 0x007c
#define SW_TURBO_1_ENC_PAUSE_NUM_OFFSET 0
#define SW_TURBO_1_ENC_PAUSE_NUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_WAROUND_CTRL_ADDR 0x0080
#define SW_TX_RST_WHEN_DONE_OFFSET 12
#define SW_TX_RST_WHEN_DONE_MASK 0x00001000
#define SW_TX_READY_PROT_EN_OFFSET 11
#define SW_TX_READY_PROT_EN_MASK 0x00000800
#define SW_FEC_CONFIG_UNDERFLOW_EN_OFFSET 10
#define SW_FEC_CONFIG_UNDERFLOW_EN_MASK 0x00000400
#define SW_FEC_FC101_UNDERFLOW_EN_OFFSET 9
#define SW_FEC_FC101_UNDERFLOW_EN_MASK 0x00000200
#define SW_FEC_FC_UNDERFLOW_EN_OFFSET 8
#define SW_FEC_FC_UNDERFLOW_EN_MASK 0x00000100
#define SW_FEC_FC_CRC_UNDERFLOW_EN_OFFSET 7
#define SW_FEC_FC_CRC_UNDERFLOW_EN_MASK 0x00000080
#define SW_FEC_PB_UNDERFLOW_EN_OFFSET 6
#define SW_FEC_PB_UNDERFLOW_EN_MASK 0x00000040
#define SW_FEC_PB_CRC_UNDERFLOW_EN_OFFSET 5
#define SW_FEC_PB_CRC_UNDERFLOW_EN_MASK 0x00000020
#define SW_TX_FD_FSM_UNDERFLOW_EN_OFFSET 4
#define SW_TX_FD_FSM_UNDERFLOW_EN_MASK 0x00000010
#define SW_TIME_OUT_EN_OFFSET 3
#define SW_TIME_OUT_EN_MASK 0x00000008
#define SW_TX_PPDU_MODE_OVERWRITE_VALUE_OFFSET 1
#define SW_TX_PPDU_MODE_OVERWRITE_VALUE_MASK 0x00000006
#define SW_TX_PPDU_MODE_OVERWRITE_EN_OFFSET 0
#define SW_TX_PPDU_MODE_OVERWRITE_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_0_ADDR 0x0090
#define SW_TX_NO_NSG_SYMB_START_DLY_OFFSET 24
#define SW_TX_NO_NSG_SYMB_START_DLY_MASK 0x7F000000
#define SW_NSG_TONE_CIRCLE_USE_CTRL_OFFSET 16
#define SW_NSG_TONE_CIRCLE_USE_CTRL_MASK 0x000F0000
#define SW_NSG_PHAS_CIRCLE_USE_CTRL_OFFSET 0
#define SW_NSG_PHAS_CIRCLE_USE_CTRL_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_1_ADDR 0x0094
#define SW_IS_1535_INSERT_PREAM_OFFSET 0
#define SW_IS_1535_INSERT_PREAM_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_2_ADDR 0x0098
#define SW_IS_511_INSERT_PREAM_OFFSET 0
#define SW_IS_511_INSERT_PREAM_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_3_ADDR 0x009c
#define SW_IS_191_INSERT_PREAM_OFFSET 0
#define SW_IS_191_INSERT_PREAM_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_4_ADDR 0x00a0
#define SW_IS_0_BITS_FIFO_EMPTY_01_OFFSET 24
#define SW_IS_0_BITS_FIFO_EMPTY_01_MASK 0x7F000000
#define SW_IS_0_BITS_FIFO_EMPTY_00_OFFSET 16
#define SW_IS_0_BITS_FIFO_EMPTY_00_MASK 0x007F0000
#define SW_IS_64_BITS_FIFO_FULL_01_OFFSET 8
#define SW_IS_64_BITS_FIFO_FULL_01_MASK 0x00007F00
#define SW_IS_64_BITS_FIFO_FULL_00_OFFSET 0
#define SW_IS_64_BITS_FIFO_FULL_00_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_5_ADDR 0x00a4
#define SW_IS_0_BITS_FIFO_EMPTY_11_OFFSET 24
#define SW_IS_0_BITS_FIFO_EMPTY_11_MASK 0x7F000000
#define SW_IS_0_BITS_FIFO_EMPTY_10_OFFSET 16
#define SW_IS_0_BITS_FIFO_EMPTY_10_MASK 0x007F0000
#define SW_IS_64_BITS_FIFO_FULL_11_OFFSET 8
#define SW_IS_64_BITS_FIFO_FULL_11_MASK 0x00007F00
#define SW_IS_64_BITS_FIFO_FULL_10_OFFSET 0
#define SW_IS_64_BITS_FIFO_FULL_10_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_6_ADDR 0x00a8
#define SW_IS_0_BITS_FIFO_EMPTY_OFFSET 8
#define SW_IS_0_BITS_FIFO_EMPTY_MASK 0x00007F00
#define SW_IS_64_BITS_FIFO_FULL_OFFSET 0
#define SW_IS_64_BITS_FIFO_FULL_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_7_ADDR 0x00ac
#define SW_IS_6_NO_NSG_RD_PB_ANOTHER_OFFSET 28
#define SW_IS_6_NO_NSG_RD_PB_ANOTHER_MASK 0x70000000
#define SW_IS_6_NO_NSG_RD_PB_OFFSET 24
#define SW_IS_6_NO_NSG_RD_PB_MASK 0x07000000
#define SW_IS_E_PB_DPSK_OFFSET 20
#define SW_IS_E_PB_DPSK_MASK 0x00F00000
#define SW_IS_A_PB_DPSK_OFFSET 16
#define SW_IS_A_PB_DPSK_MASK 0x000F0000
#define SW_IS_8_PB_DPSK_OFFSET 12
#define SW_IS_8_PB_DPSK_MASK 0x0000F000
#define SW_IS_6_PB_DPSK_OFFSET 8
#define SW_IS_6_PB_DPSK_MASK 0x00000F00
#define SW_IS_2_PB_DPSK_OFFSET 4
#define SW_IS_2_PB_DPSK_MASK 0x000000F0
#define SW_IS_0_PB_DPSK_OFFSET 0
#define SW_IS_0_PB_DPSK_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_8_ADDR 0x00b0
#define SW_IS_1_BGZLA_182_FIX_OFFSET 20
#define SW_IS_1_BGZLA_182_FIX_MASK 0x7FF00000
#define SW_IS_E_FC_DPSK_OFFSET 16
#define SW_IS_E_FC_DPSK_MASK 0x000F0000
#define SW_IS_A_FC_DPSK_OFFSET 12
#define SW_IS_A_FC_DPSK_MASK 0x0000F000
#define SW_IS_6_FC_DPSK_OFFSET 8
#define SW_IS_6_FC_DPSK_MASK 0x00000F00
#define SW_IS_2_FC_DPSK_OFFSET 4
#define SW_IS_2_FC_DPSK_MASK 0x000000F0
#define SW_IS_0_FC_DPSK_OFFSET 0
#define SW_IS_0_FC_DPSK_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_A_ADDR 0x00b8
#define SW_IS_4_FOR_BUF_SWITCH_JUDGE_OFFSET 16
#define SW_IS_4_FOR_BUF_SWITCH_JUDGE_MASK 0x00070000
#define SW_HYBRID_BUFFER_SWITCH_SYMB_NUM_OFFSET 8
#define SW_HYBRID_BUFFER_SWITCH_SYMB_NUM_MASK 0x00000700
#define SW_HYBRID_FC_SYMB_NUM_OFFSET 0
#define SW_HYBRID_FC_SYMB_NUM_MASK 0x00000007

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_C_ADDR 0x00c0
#define SW_RI_POINT_NUM_OFFSET 11
#define SW_RI_POINT_NUM_MASK 0x007FF800
#define SW_FC101_GI_OFFSET_OFFSET 0
#define SW_FC101_GI_OFFSET_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_D_ADDR 0x00c4
#define SW_SG_IFFT_POINT_NUM_HALF_OFFSET 13
#define SW_SG_IFFT_POINT_NUM_HALF_MASK 0x01FFE000
#define SW_SG_IFFT_POINT_NUM_OFFSET 0
#define SW_SG_IFFT_POINT_NUM_MASK 0x00001FFF

//-----------------------------------
#define CFG_BB_TX_CONST_CTRL_E_ADDR 0x00c8
#define SW_RI_FORMULA_CHOS_OFFSET 27
#define SW_RI_FORMULA_CHOS_MASK 0x08000000
#define SW_RI_DIVIDE_MODE_OFFSET 24
#define SW_RI_DIVIDE_MODE_MASK 0x07000000
#define SW_GP_PREAM_IFFT_POINT_NUM_HALF_OFFSET 12
#define SW_GP_PREAM_IFFT_POINT_NUM_HALF_MASK 0x00FFF000
#define SW_GP_PREAM_IFFT_POINT_NUM_OFFSET 0
#define SW_GP_PREAM_IFFT_POINT_NUM_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_TX_FREQ_SEL_CTRL_ADDR 0x00cc
#define SW_TX_FD_TD_FREQ_SEL_OFFSET 4
#define SW_TX_FD_TD_FREQ_SEL_MASK 0x00000010
#define SW_TX_FD_FFT_FREQ_SEL_OFFSET 0
#define SW_TX_FD_FFT_FREQ_SEL_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_PWR_FROM_MAC_CTRL_ADDR 0x00d0
#define SW_NSG_EXPAND_RELETIVE_PWR_SIGN_OFFSET 16
#define SW_NSG_EXPAND_RELETIVE_PWR_SIGN_MASK 0x00010000
#define SW_NSG_EXPAND_RELETIVE_PWR_OFFSET 8
#define SW_NSG_EXPAND_RELETIVE_PWR_MASK 0x00007F00
#define SW_TX_PWR_ANA_FROM_TX_DESC_OFFSET 2
#define SW_TX_PWR_ANA_FROM_TX_DESC_MASK 0x00000004
#define SW_TX_PWR_TD_FROM_TX_DESC_OFFSET 1
#define SW_TX_PWR_TD_FROM_TX_DESC_MASK 0x00000002
#define SW_TX_PWR_FD_FROM_TX_DESC_OFFSET 0
#define SW_TX_PWR_FD_FROM_TX_DESC_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_VECTOR_FORCE_0_ADDR 0x00d4
#define SW_FORCE_TX_MAC_PB_NUM_OFFSET 1
#define SW_FORCE_TX_MAC_PB_NUM_MASK 0x000007FE
#define SW_FORCE_TX_MAC_PB_NUM_EN_OFFSET 0
#define SW_FORCE_TX_MAC_PB_NUM_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_VECTOR_FORCE_1_ADDR 0x00d8
#define SW_FORCE_TX_POWER_TD_OFFSET 25
#define SW_FORCE_TX_POWER_TD_MASK 0x3E000000
#define SW_FORCE_TX_POWER_TD_EN_OFFSET 24
#define SW_FORCE_TX_POWER_TD_EN_MASK 0x01000000
#define SW_FORCE_TX_POWER_ANA_OFFSET 17
#define SW_FORCE_TX_POWER_ANA_MASK 0x000E0000
#define SW_FORCE_TX_POWER_ANA_EN_OFFSET 16
#define SW_FORCE_TX_POWER_ANA_EN_MASK 0x00010000
#define SW_FORCE_TX_POWER_FD_FRAC_OFFSET 9
#define SW_FORCE_TX_POWER_FD_FRAC_MASK 0x00001E00
#define SW_FORCE_TX_POWER_FD_FRAC_EN_OFFSET 8
#define SW_FORCE_TX_POWER_FD_FRAC_EN_MASK 0x00000100
#define SW_FORCE_TX_POWER_FD_INT_OFFSET 1
#define SW_FORCE_TX_POWER_FD_INT_MASK 0x000000FE
#define SW_FORCE_TX_POWER_FD_INT_EN_OFFSET 0
#define SW_FORCE_TX_POWER_FD_INT_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_FC101_CONST_CTRL_ADDR 0x00dc
#define SW_TX_FC101_END_TONE_OFFSET 12
#define SW_TX_FC101_END_TONE_MASK 0x007FF000
#define SW_TX_FC101_START_TONE_OFFSET 0
#define SW_TX_FC101_START_TONE_MASK 0x000007FF

//-----------------------------------
#define CFG_BB_TX_FC101_OFFSET_CTRL_ADDR 0x00e0
#define SW_TX_FC101_ITLV_OFFSET_3_OFFSET 24
#define SW_TX_FC101_ITLV_OFFSET_3_MASK 0x7F000000
#define SW_TX_FC101_ITLV_OFFSET_2_OFFSET 16
#define SW_TX_FC101_ITLV_OFFSET_2_MASK 0x007F0000
#define SW_TX_FC101_ITLV_OFFSET_1_OFFSET 8
#define SW_TX_FC101_ITLV_OFFSET_1_MASK 0x00007F00
#define SW_TX_FC101_ITLV_OFFSET_0_OFFSET 0
#define SW_TX_FC101_ITLV_OFFSET_0_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_TX_INT_EN_ADDR 0x00e4
#define BB_TX_INT_EN_OFFSET 0
#define BB_TX_INT_EN_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_INT_CLR_ADDR 0x00e8
#define BB_TX_INT_CLR_OFFSET 0
#define BB_TX_INT_CLR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_INT_MASK_ADDR 0x00ec
#define BB_TX_INT_MASK_OFFSET 0
#define BB_TX_INT_MASK_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_INT_RAW_ADDR 0x00f0
#define BB_TX_INT_RAW_OFFSET 0
#define BB_TX_INT_RAW_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FD_TIMEOUT_TH_0_ADDR 0x00f4
#define SW_FD_TIME_TH_PREAM_OFFSET 16
#define SW_FD_TIME_TH_PREAM_MASK 0xFFFF0000
#define SW_FD_TIME_TH_FC_OFFSET 0
#define SW_FD_TIME_TH_FC_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_TX_FD_TIMEOUT_TH_1_ADDR 0x00f8
#define SW_FD_TIME_TH_FC101_OFFSET 16
#define SW_FD_TIME_TH_FC101_MASK 0xFFFF0000
#define SW_FD_TIME_TH_PLD_OFFSET 0
#define SW_FD_TIME_TH_PLD_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_TX_FD_TIMEOUT_TH_2_ADDR 0x00fc
#define SW_FD_TIME_TH_WAIT_TD_DONE_OFFSET 16
#define SW_FD_TIME_TH_WAIT_TD_DONE_MASK 0xFFFF0000
#define SW_FD_TIME_TH_IFFT_OFFSET 0
#define SW_FD_TIME_TH_IFFT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_TX_FEC_TIMEOUT_TH_0_ADDR 0x0100
#define SW_FEC_TIMEOUT_TH_CONFIG_OFFSET 16
#define SW_FEC_TIMEOUT_TH_CONFIG_MASK 0xFFFF0000
#define SW_FEC_TIMEOUT_TH_FC101_OFFSET 0
#define SW_FEC_TIMEOUT_TH_FC101_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_TX_FEC_TIMEOUT_TH_1_ADDR 0x0104
#define SW_FEC_TIMEOUT_TH_FC_OFFSET 16
#define SW_FEC_TIMEOUT_TH_FC_MASK 0xFFFF0000
#define SW_FEC_TIMEOUT_TH_FC_CRC_OFFSET 0
#define SW_FEC_TIMEOUT_TH_FC_CRC_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_TX_FEC_TIMEOUT_TH_2_ADDR 0x0108
#define SW_FEC_TIMEOUT_TH_PB_OFFSET 10
#define SW_FEC_TIMEOUT_TH_PB_MASK 0xFFFFFC00
#define SW_FEC_TIMEOUT_TH_PB_CRC_OFFSET 0
#define SW_FEC_TIMEOUT_TH_PB_CRC_MASK 0x000003FF

//-----------------------------------
#define CFG_BB_TX_TURBO_ENC_RESULT_ICG_ADDR 0x010c
#define SW_TURBO1_REG_1300_ICG_EN_OFFSET 1
#define SW_TURBO1_REG_1300_ICG_EN_MASK 0x00000002
#define SW_TURBO0_REG_1300_ICG_EN_OFFSET 0
#define SW_TURBO0_REG_1300_ICG_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_CTRL_ADDR 0x0110
#define SW_TX_ABORT_DBG_CLR_OFFSET 7
#define SW_TX_ABORT_DBG_CLR_MASK 0x00000080
#define SW_FC_SYMB_DONE_RST_CHOS_OFFSET 6
#define SW_FC_SYMB_DONE_RST_CHOS_MASK 0x00000040
#define SW_TX_TD_DONE_SRST_TX_FD_EN_OFFSET 5
#define SW_TX_TD_DONE_SRST_TX_FD_EN_MASK 0x00000020
#define SW_DBG_DOUBLE_TX_START_CLR_OFFSET 4
#define SW_DBG_DOUBLE_TX_START_CLR_MASK 0x00000010
#define SW_TD_SYMB_DONE_CHOS_OFFSET 3
#define SW_TD_SYMB_DONE_CHOS_MASK 0x00000008
#define SW_FEC_TIMEOUT_EN_OFFSET 2
#define SW_FEC_TIMEOUT_EN_MASK 0x00000004
#define SW_FEC_TX_UNDERFLOW_EN_OFFSET 1
#define SW_FEC_TX_UNDERFLOW_EN_MASK 0x00000002
#define SW_TX_ABORT_DBG_LOCK_CLR_OFFSET 0
#define SW_TX_ABORT_DBG_LOCK_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_0_ADDR 0x0114
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_OFFSET 0
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_1_ADDR 0x0118
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_OFFSET 0
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_2_ADDR 0x011c
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_2_OFFSET 0
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_3_ADDR 0x0120
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_2_OFFSET 0
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_FD_SPARE_BUS_ADDR 0x0124
#define TX_FD_SPARE_OUT_OFFSET 0
#define TX_FD_SPARE_OUT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_4_ADDR 0x0128
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_4_OFFSET 0
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_5_ADDR 0x012c
#define RO_DOUBLE_TX_START_CNT_OFFSET 0
#define RO_DOUBLE_TX_START_CNT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_6_ADDR 0x0130
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_6_OFFSET 0
#define FEC_TOP_DBG_LOCK_FOR_TX_ABORT_6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_TX_ABORT_DBG_STS_7_ADDR 0x0134
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_7_OFFSET 0
#define TX_FSM_DBG_BUS_LOCK_FOR_TX_ABORT_7_MASK 0xFFFFFFFF

//HW module read/write macro
#define PHY_TX_READ_REG(addr) SOC_READ_REG(PHY_TX_BASEADDR + addr)
#define PHY_TX_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_TX_BASEADDR + addr,value)